MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 337

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

17.5.1.1.2
Unlike transmit, the length of the receive frame is unknown by the driver ahead of time. Therefore, the
driver must set a variable to define the length of all receive buffers. In the FEC, this variable is written to
the EMRBR register.
The driver (RxBD software producer) should set up some number of empty buffers for the Ethernet by
initializing the address field and the E and W bits of the associated receive BDs. The hardware (receive
DMA) consumes these buffers by filling them with data as frames are received and clearing the E bit and
writing to the L bit (1 indicates last buffer in frame), the frame status bits (if L is set), and the length field.
If a receive frame spans multiple receive buffers, the L bit is only set for the last buffer in the frame. For
non-last buffers, the length field in the receive BD is written by the DMA (at the same time the E bit is
cleared) with the default receive buffer length value. For end-of-frame buffers, the receive BD is written
with L set and information written to the status bits (M, BC, MC, LG, NO, CR, OV, TR). Some of the status
bits are error indicators which, if set, indicate the receive frame should be discarded and not given to higher
layers. The frame status/length information is written into the receive FIFO following the end of the frame
(as a single 32-bit word) by the receive logic. The length field for the end of frame buffer is written with
the length of the entire frame, not only the length of the last buffer.
For simplicity, the driver may assign a large enough default receive buffer length to contain an entire
frame, keeping in mind that a malfunction on the network or out-of-spec implementation could result in
giant frames. Frames of 2K (2048) bytes or larger are truncated by the FEC at 2047 bytes so software never
sees a receive frame larger than 2047 bytes.
Similar to transmit, the FEC polls the receive descriptor ring after the driver sets up receive BDs and writes
to the RDAR register. As frames are received, the FEC fills receive buffers and updates the associated BDs,
then reads the next BD in the receive descriptor ring. If the FEC reads a receive BD and finds the E bit
cleared, it polls this BD once more. If RxBD[E] is clear a second time, FEC stops reading receive BDs
until the driver writes to RDAR.
17.5.1.2
In the RxBD, the user initializes the E and W bits in the first longword and the pointer in the second
longword. When the buffer has been DMA’d, the Ethernet controller modifies the E, L, M, BC, MC, LG,
NO, CR, OV, and TR bits and writes the length of the used portion of the buffer in the first longword. The
M, BC, MC, LG, NO, CR, OV, and TR bits in the first longword of the buffer descriptor are only modified
by the Ethernet controller when the L bit is set.
Freescale Semiconductor
Offset + 0
Offset + 2
Offset + 4
Offset + 6
Ethernet Receive Buffer Descriptor (RxBD)
15
E
Driver/DMA Operation with Receive BDs
RO1
14
13
W
Figure 17-25. Receive Buffer Descriptor (RxBD)
RO2
12
11
L
—
10
Rx Data Buffer Pointer - A[31:16]
Rx Data Buffer Pointer - A[15:0]
—
9
Data Length
M
8
BC
7
MC
6
LG
5
NO
4
Fast Ethernet Controller (FEC)
—
3
CR
2
OV
1
TR
0
17-27