MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 505

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor
AN[56:55:53:52]
(Pin Name)
QSPI_DOUT
DDATA[3:0]
QSPI_CLK
Function
QSPI_DIN
QSPI_CS
Primary
A[23:21]
IRQ[7:1]
AN[3:0]
PST[3:0]
BS[3:0]
CS[3:0]
D[31:0]
A[20:0]
CANRX
CANTX
SRAS
SIZ1
SIZ0
TEA
R/W
TIP
SDA
OE
SCL
[3:0]
TS
TA
2
1
1
1
1
1
1
1
1
2
1
1
1
2
1
3
1
Function)
(Default
PDD[7:4]
PDD[7:4]
PNQ[7:1]
PQB[3:0]
PQS[6:3]
[4:3:1:0]
PF[4:0],
PA, PB,
PC, PD
PG, PH
PF[7:5]
PQS[2]
PQS[1]
PQS[0]
PJ[7:4]
PJ[3:0]
PSD[5]
PAS[3]
PAS[2]
PAS[1]
PAS[0]
GPIO
PE[7]
PE[6]
PE[5]
PE[4]
PE[3]
PE[2]
PE[1]
PE[0]
PQA
Function 1
ETRIG[2:1],
ANX, ANW
Alternate
ANZ, ANY,
SYNCA
SYNCB
SYNCA
SYNCB
URXD2
MA[1:0]
CS[6:4]
URXD2
UTXD2
UTXD2
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Table 26-1. Ports External Signals
Function 2
Alternate
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External data bus / Ports A, B, C, D
Output enable for external reads / Port E[7]
Transfer acknowledge for external data transfer / Port E[6]
Transfer error acknowledge for external data transfer / Port E[5]
Read/Write indication for external data transfer / Port E[4]
Size of the external data transfer / Port E[3] / Timer A sync
Size of the external data transfer / Port E[3:2] / Timer B sync
Transfer start indication for external data transfer / Port E[1] /
Timer A sync
Transfer in progress indication for external data transfer / Port
E[0] / Timer B sync
External address bus [23:21] / Port F[7:5] / Chip selects 6–4
External address bus [20:0] / Ports F[4:0], G, H
Byte strobes for external data transfer / Port J[7:4] / SDRAM
column address strobes
Chip selects 3 - 0 / Port J[3:0]
Debug data / Port DD[7:4]
Processor status / Port DD[3:0]
FlexCAN receive data / Port AS[3] / URXD2
FlexCAN transmit data / Port AS[2] / UTXD2
I
I
Edge Port external interrupt pins / Port NQ[7:1]
QADC analog inputs / Port QA[4:3:1:0] / external triggers /
external multiplex control
QADC analog inputs / Port QB[3:0] / multiplexed analog inputs
QSPI synchronous peripheral chip selects / Port QS[3:6]
QSPI serial clock / Port QS[2]
QSPI serial data input / Port QS[1]
QSPI serial data output / Port QS[0]
SDRAM synchronous row address strobe / Port SD[5]
2
2
C serial data / Port AS[1] / URXD2
C serial clock / Port AS[0] / UTXD2
Description
General Purpose I/O Module
26-5