EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 107

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
July 2005
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Clock multiplication and division
Phase shift
Delay shift
Clock switchover
PLL reconfiguration
Programmable bandwidth
Spread spectrum clocking
Programmable duty cycle
Number of internal clock outputs
Number of external clock outputs
Number of feedback clock inputs
Table 2–19. Stratix PLL Features
For enhanced PLLs, m, n, range from 1 to 512 and post-scale counters g, l, e range from 1 to 1024 with 50% duty
cycle. With a non-50% duty cycle the post-scale counters g, l, e range from 1 to 512.
For fast PLLs, m and post-scale counters range from 1 to 32.
The smallest phase shift is determined by the voltage controlled oscillator (VCO) period divided by 8.
For degree increments, Stratix devices can shift all output frequencies in increments of at least 45 . Smaller degree
increments are possible depending on the frequency and divide parameters.
PLLs 7, 8, 9, and 10 have two output ports per PLL. PLLs 1, 2, 3, and 4 have three output ports per PLL.
Every Stratix device has two enhanced PLLs (PLLs 5 and 6) with either eight single-ended outputs or four
differential outputs each. Two additional enhanced PLLs (PLLs 11 and 12) in EP1S80, EP1S60, and EP1S40 devices
each have one single-ended output. Devices in the 780 pin FineLine BGA packages do not support PLLs 11 and 12.
Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data
channel to generate txclkout.
Every Stratix device has two enhanced PLLs with one single-ended or differential external feedback input per PLL.
Table
Feature
2–19:
Table 2–19
devices.
Down to 156.25-ps increments (3),
Four differential/eight singled-ended
m/(n
250-ps increments for ±3 ns
shows the enhanced PLL and fast PLL features in Stratix
or one single-ended
post-scale counter)
Enhanced PLL
2
v
v
v
v
v
6
(8)
(6)
(1)
(4)
Stratix Device Handbook, Volume 1
Down to 125-ps increments (3),
m/(post-scale counter)
Fast PLL
3
Stratix Architecture
v
(7)
(5)
(2)
2–83
(4)