EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 756

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Configuration Schemes
11–38
Stratix Device Handbook, Volume 2
During JTAG configuration, data is downloaded to the device on the PCB
through the MasterBlaster or ByteBlasterMV header. Configuring devices
through a cable is similar to programming devices in-system. One
difference is to connect the TRST pin to V
controller is not reset. See
Figure 11–20. JTAG Configuration of a Single Device
Notes to
(1)
(2)
(3)
To configure a single device in a JTAG chain, the programming software
places all other devices in BYPASS mode. In BYPASS mode, devices pass
programming data from the TDI pin to the TDO pin through a single
bypass register without being affected internally. This scheme enables the
programming software to program or verify the target device.
Configuration data driven into the device appears on the TDO pin one
clock cycle later.
V CC
10 kΩ
You should connect the pull-up resistor to the same supply voltage as the
download cable.
You should connect the nCONFIG, MSEL0, and MSEL1 pins to support a non-JTAG
configuration scheme. If you only use JTAG configuration, connect nCONFIG to
V
low.
V
device’s V
this value.
CC
IO
V CC
is a reference voltage for the MasterBlaster output driver. V
, and MSEL0, MSEL1, and MSEL2 to ground. Pull DATA0 and DCLK to high or
Figure
10 kΩ
(2)
(2)
GND
(2)
(2)
(2)
(2)
V CC
CCIO
11–20:
. See the MasterBlaster Serial/USB Communications Cable Data Sheet for
nCE
TRST
nSTATUS
CONF_DONE
nCONFIG
MSEL0
MSEL1
MSEL2
DATA0
DCLK
Stratix GX Device
Stratix or
Figure
TDO
TMS
TCK
TDI
11–20.
1 kΩ
V CC (1)
CC
V CC (1)
to ensure that the TAP
1 kΩ
1 kΩ
GND
MasterBlaster or ByteBlasterMV
Pin 1
Altera Corporation
IO
10-Pin Male Header
should match the
(Top View)
GND
July 2005
V CC (1)
VIO (3)
GND