EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 657

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
July 2005
PMA_RX_CLK
Data set-up time (T
Data hold time (T
PCS sampling window
RSKM (WAN)
RSKM (LAN)
Table 8–5. PCS Receiver Timing Specifications (Part 2 of 2)
duty cycle
hold
setup
Parameter
)
)
XGMII
The purpose of XGMII is to provide a simple, inexpensive, and easy to
implement interconnection between the MAC sublayer and the PHY.
Though XGMII is an optional interface, it is used extensively in the
10-Gigabit Ethernet standard as the basis for the specification. The
conversion between the parallel data paths of XGMII and the serial MAC
data stream is carried out by the reconciliation sublayer. The
reconciliation sublayer maps the signal set provided at the XGMII to the
physical layer signaling (PLS) service primitives provided at the MAC.
XGMII supports a 10-Gbps MAC data rate.
Functional Description
The XGMII is composed of independent transmit and receive paths. Each
direction uses 32 data signals, TXD[31..0] and RXD[31..0], 4 control
signals, TXC[3..0] and RXC[3..0], and a clock TX_CLK and RX_CLK.
Figure 8–10
Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices
shows the XGMII functional block diagram.
Min
300
300
600
45
Value
Typ
Stratix Device Handbook, Volume 2
Max
304
276
55
Unit
ps
ps
ps
ps
ps
%
8–13