EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 773

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
July 2005
nCEO
DCLK
DATA0
Table 11–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device
Pin Name
N/A
N/A
I/O
User Mode
All Multi-
Device
Schemes
Synchronous
configuration
schemes
(PS, FPP)
PS, FPP, PPA Input
Configuration
Scheme
Output
Input
(PS, FPP)
Pin Type
Output that drives low when device
configuration is complete. In single device
configuration, this pin is left floating. In multi-
device configuration, this pin feeds the next
device’s
in the chain is left floating.
The voltage levels driven out by this pin are
dependent on the V
resides in.
In PS and FPP configuration,
input used to clock data from an external
source into the target device. Data is latched
into the FPGA on the rising edge of
In PPA mode,
to prevent this pin from floating.
After configuration, this pin is tri-stated. In
schemes that use a configuration device,
DCLK
In schemes that use a control host,
should be driven either high or low, whichever
is more convenient. Toggling this pin after
configuration does not affect the configured
device. This pin uses Schmitt trigger input
buffers.
Data input. In serial configuration modes, bit-
wide configuration data is presented to the
target device on the
V
V
After configuration,
user I/O and the state of this pin depends on
the Dual-Purpose Pin settings.
After configuration, EPC1 and EPC1441
devices tri-state this pin, while enhanced
configuration and EPC2 devices drive this pin
high.
I L
C C I O
Configuring Stratix & Stratix GX Devices
levels for this pin are dependent on the
is driven low after configuration is done.
of the I/O bank that it resides in.
nCE
Stratix Device Handbook, Volume 2
pin. The
DCLK
Description
DATA0
C C I O
should be tied high to V
DATA0
(Part 5 of 8)
nCEO
of the I/O bank it
is available as a
pin. The V
of the last device
DCLK
is the clock
DCLK
DCLK
I H
11–55
and
.
C C