EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 311

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Introduction
Altera Corporation
July 2005
Notes to
(1)
(2)
(3)
EP1S10
EP1S20
EP1S25
EP1S30
EP1S40
EP1S60
EP1S80
S52001-3.2
Device
Table 1–1. Stratix Device PLL Availability
PLLs 5 and 6 each have eight single-ended outputs or four differential outputs.
PLLs 11 and 12 each have one single-ended output.
EP1S30 and EP1S40 devices do not support these PLLs in the 780-pin FineLine BGA
Table
v
v
v
v
v
v
v
1
1–1:
v
v
v
v
v
v
v
2
v
v
v
v
v
v
v
3
Stratix
(PLLs) that provide robust clock management and synthesis for on-chip
clock management, external system clock management, and high-speed
I/O interfaces. There are two types of PLLs in each Stratix and Stratix GX
device: enhanced PLLs and fast PLLs. Each device has up to four
enhanced PLLs, which are feature-rich, general-purpose PLLs supporting
advanced capabilities such as external feedback, clock switchover, phase
and delay control, PLL reconfiguration, spread spectrum clocking, and
programmable bandwidth. There are also up to eight fast PLLs per
device, which offer general-purpose clock management with
multiplication and phase shifting as well as high-speed outputs to
manage the high-speed differential I/O interfaces.
The Altera
without requiring any external devices.
Tables 1–1
devices, respectively.
v
v
v
v
v
v
v
4
v
v
®
Fast PLLs
v
v
and Stratix GX devices have highly versatile phase-locked loops
7
(3)
(3)
®
and
Quartus
v
v
1–2
v
v
8
(3)
(3)
1. General-Purpose PLLs in
Stratix & Stratix GX Devices
show PLL availability for Stratix and Stratix GX
®
II software enables the PLLs and their features
v
v
v
v
9
(3)
(3)
v
v
10
v
v
(3)
(3)
5(1)
v
v
v
v
v
v
v
®
package.
Enhanced PLLs
6(1)
v
v
v
v
v
v
v
v
11(2)
v
v
(3)
v
12(2)
v
v
(3)
1–1