EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 635

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Figure 7–35. Block Diagram on Serial Implementation of 2-D DCT
Altera Corporation
September 2004
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
points in parallel. There is also a parallel-to-serial conversion block at the
output because the column processing stage generates the output image
column-by-column. In order to have the output in the same order as the
input (i.e., row-by-row), this conversion is necessary. Appropriate scaling
needs to be applied to the completed transform but this can be combined
with the quantization stage which often follows a DCT [1].
shows a top-level block diagram of this design.
The implementation of the 1-D DCT block is based on the algorithm
shown in
stages 1, 2 and 3 are implemented using logic cells. The multiply and
multiply-addition operations in stage 4 are implemented using DSP
blocks in the Stratix device in the simple multiplier mode, two-multiplier
adder mode, and the four-multiplier adder mode. An example of the
multiply-addition block is shown in
Figure
7–33. The simple addition and subtraction operations in
Figure
Stratix Device Handbook, Volume 2
7–36.
Figure 7–35
7–57