EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 406

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

DDR Memory Support Overview
DDR Memory
Support
Overview
3–10
Stratix Device Handbook, Volume 2
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
DDR SDRAM (1),
(2)
DDR SDRAM - side
banks (2), (3),
RLDRAM II
QDR SRAM
QDRII SRAM
ZBT SRAM
DDR SDRAM (1),
DDR SDRAM - side banks (2),
QDR SRAM
QDRII SRAM
DDR Memory Type
Table 3–1. External RAM Support in Stratix EP1S10 through EP1S40 & All Stratix GX Devices
Table 3–2. External RAM Support in Stratix EP1S60 & EP1S80 (Part 1 of 2)
These maximum clock rates apply if the Stratix device uses DQS phase-shift circuitry to interface with DDR
SDRAM. DQS phase-shift circuitry is only available on the top and bottom I/O banks (I/O banks 3, 4, 7, and 8).
For more information on DDR SDRAM, see AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices.
DDR SDRAM is supported on the Stratix device side I/O banks (I/O banks 1, 2, 5, and 6) without dedicated DQS
phase-shift circuitry. The read DQS signal is ignored in this mode.
These performance specifications are preliminary.
This device does not support RLDRAM II.
For more information on QDR or QDRII SRAM, see AN 349: QDR SRAM Controller Reference Design for Stratix &
Stratix GX Devices.
For more information on ZBT SRAM, see AN 329: ZBT SRAM Controller Reference Design for Stratix and Stratix GX
Devices.
DDR Memory Type
Table
(4)
(7)
(6)
(4)
(6)
(4)
(4)
3–1:
(2)
SSTL-2
SSTL-2
1.8-V HSTL
1.5-V HSTL
1.5-V HSTL
LVTTL
Standard
I/O
Table 3–1
EP1S40 devices and all Stratix GX devices.
RAM support in Stratix EP1S60 and EP1S80 devices.
(3)
SSTL-2
SSTL-2
1.5-V HSTL
1.5-V HSTL
Flip-Chip Flip-Chip
-5 Speed
Grade
I/O Standard
200
150
200
167
200
200
shows the external RAM support in Stratix EP1S10 through
-6 Speed Grade
167
133
167
167
200
(5)
-5 Speed Grade
Maximum Clock Rate (MHz)
Wire-
Bond
133
110
133
133
200
167
150
133
167
(5)
Maximum Clock Rate (MHz)
-7 Speed Grade
Flip-
Chip
133
133
133
133
167
(5)
-6 Speed Grade -7 Speed Grade
Table 3–2
167
133
133
167
Wire-
Bond
100
100
100
100
167
(5)
shows the external
Altera Corporation
-8 Speed Grade
Flip-
Chip
100
100
100
100
133
(5)
133
133
133
133
June 2006
Wire-
Bond
100
100
100
100
133
(5)