EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 479

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
July 2005
Stratix Differential I/O Receiver Operation
You can configure any of the Stratix differential input channels as a
receiver channel (see
the incoming high-speed data. The input shift register continuously
clocks the incoming data on the negative transition of the high-frequency
clock generated by the PLL clock (
The data in the serial shift register is shifted into a parallel register by the
RXLOADEN signal generated by the fast PLL counter circuitry on the third
falling edge of the high-frequency clock. However, you can select which
falling edge of the high frequency clock loads the data into the parallel
register, using the data-realignment circuit. For more information on the
data-realignment circuit, see
on page
In normal mode, the enable signal RXLOADEN loads the parallel data into
the next parallel register on the second rising edge of the low-frequency
clock. You can also load data to the parallel register through the
TXLOADEN signal when using the data-realignment circuit.
Figure 5–3
Figure 5–4
Stratix devices in
data parallelization division factor.
5–25.
shows the block diagram of a single SERDES receiver channel.
shows the timing relationship between the data and clocks in
×
10 mode. W is the low-frequency multiplier and J is
High-Speed Differential I/O Interfaces in Stratix Devices
Figure
5–3). The differential receiver deserializes
“Data Realignment Principles of Operation”
×
W).
Stratix Device Handbook, Volume 2
5–7