EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 619

IC STRATIX FPGA 10K LE 484-FBGA

EP1S10F484I6

Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheets

Specifications of EP1S10F484I6

Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant

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Altera Corporation
September 2004
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Through the use of integer feedforward multiplies, which can be
implemented by combining addition, shifting, and complimenting
operations, a Butterworth filter’s transfer function biquad can be
optimized for logic synthesis. The most efficient transformation is that of
an all pole filter. This is because there is a unique relationship between the
feedforward integer coefficients of the filter represented as:
As can be seen by this equation, the z
(representing the feedforward path) is twice the other two operands (z
and 1). This is always the case in the transformation from the frequency
to the digital domain. This represents the normalized response, which is
faster and smaller to implement in hardware than real multipliers. It
introduces a scaling factor as well, but this can be corrected at the end of
the cascade chain through a single multiply.
Figure 7–24
Stratix or Stratix GX device.
H z
=
shows how a Butterworth filter biquad is implemented in a
------------------------------------------ -
1
1
+
+
b
1
2z
z
1 –
1 –
+
+
b
z
2
2 –
z
2 –
-1
Stratix Device Handbook, Volume 2
coefficient in the numerator
7–41
-2

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