EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 295

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Chapter Revision Dates ......................................................................... xiii
About This Handbook ............................................................................. xv
Section I. Clock Management
Chapter 1. General-Purpose PLLs in Stratix & Stratix GX Devices
Altera Corporation
How to Find Information ...................................................................................................................... xv
How to Contact Altera ........................................................................................................................... xv
Typographic Conventions .................................................................................................................... xvi
Revision History ....................................................................................................................... Section I–1
Introduction ............................................................................................................................................ 1–1
Enhanced PLLs ....................................................................................................................................... 1–5
Fast PLLs ............................................................................................................................................... 1–31
Clocking ................................................................................................................................................ 1–39
Board Layout ........................................................................................................................................ 1–50
Clock Multiplication & Division .................................................................................................... 1–9
External Clock Outputs ................................................................................................................. 1–10
Clock Feedback ............................................................................................................................... 1–14
Phase Shifting ................................................................................................................................. 1–14
Lock Detect ...................................................................................................................................... 1–15
Programmable Duty Cycle ........................................................................................................... 1–16
General Advanced Clear & Enable Control ............................................................................... 1–16
Programmable Bandwidth ............................................................................................................ 1–18
Clock Switchover ............................................................................................................................ 1–25
Spread-Spectrum Clocking ........................................................................................................... 1–25
PLL Reconfiguration ...................................................................................................................... 1–30
Enhanced PLL Pins ........................................................................................................................ 1–30
Clock Multiplication & Division .................................................................................................. 1–34
External Clock Outputs ................................................................................................................. 1–34
Phase Shifting ................................................................................................................................. 1–35
Programmable Duty Cycle ........................................................................................................... 1–36
Control Signals ................................................................................................................................ 1–36
Pins ................................................................................................................................................... 1–37
Global & Hierarchical Clocking ................................................................................................... 1–39
Clock Input Connections ............................................................................................................... 1–41
Clock Output Connections ............................................................................................................ 1–43
VCCA & GNDA ............................................................................................................................. 1–50
Contents
iii