MC7448VU1700LD Freescale Semiconductor, MC7448VU1700LD Datasheet - Page 16

• Manufacturer Part Number: MC7448VU1700LD
• Description: IC MPU RISC 32BIT 360-FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC7448VU1700LD

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 1.7GHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 360-FCCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Electrical and Thermal Characteristics
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0:5] settings must be chosen such that the resulting SYSCLK (bus)
2. Actual maximum system bus frequency is system-dependent. See
3. Rise and fall times for the SYSCLK input measured from 0.4 to 1.4 V
4. Timing is guaranteed by design and characterization.
5. Guaranteed by design
6. The SYSCLK driver’s closed loop jitter bandwidth should be less than 1.5 MHz at –3 dB.
7. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for PLL
8. This reflects the maximum and minimum core frequencies when the dynamic frequency switching feature (DFS) is disabled.
9.This specification supports the Dynamic Frequency Switching (DFS) feature and is applicable only when one of the DFS modes
10.Use of the DFS feature does not affect VCO frequency.
16
At recommended operating conditions. See
Processor
core
frequency
VCO frequency
SYSCLK frequency
SYSCLK cycle time
SYSCLK rise and fall time
SYSCLK duty cycle measured at
OV
SYSCLK cycle-to-cycle jitter
Internal PLL relock time
frequency, processor core frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to the PLL_CFG[0:5] signal description in
PLL_CFG[0:5] settings.
lock after a stable V
the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted
for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
f
(divide-by-2 or divide-by-4) is enabled. When DFS is disabled, the core frequency must conform to the maximum and minimum
frequencies stated for f
core_DFS
DD
/2
Characteristic
provides the maximum and minimum core frequencies when operating in a DFS mode.
DFS mode disabled
DFS mode enabled
DD
core
and SYSCLK are reached during the power-on reset sequence. This specification also applies when
.
MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4
Symbol
f
f
t
t
t
core
SYSCLK
SYSCLK
SYSCLK
KR
t
f
KHKL
f
VCO
core
Table
Table 8. Clock AC Timing Specifications
, t
_
KF
DF
/
4.
Min
600
300
600
5.0
1000 MHz
33
40
—
—
—
Maximum Processor Core Frequency (Speed Grade)
1000
1000
Max
500
200
100
150
0.5
30
60
Min
600
300
600
5.0
1420 MHz
33
40
—
—
—
Section 5.2.1, “Clock AC Specifications.”
1420
1420
Max
710
200
150
100
0.5
30
60
Section 9.1.1, “PLL Configuration,”
Min
600
300
600
5.0
1600 MHz
33
40
—
—
—
1600
Max
800
800
200
150
100
0.5
30
60
Min
600
300
600
5.0
1700 MHz
33
40
—
—
—
Freescale Semiconductor
1700
1700
Max
850
200
150
100
0.5
30
60
for valid
MHz
MHz
MHz
Unit
ns
ns
ps
μs
%
Notes
1, 2, 8
1, 10
1, 8
5, 6
9
2
3
4
7