MC7448VU1700LD Freescale Semiconductor, MC7448VU1700LD Datasheet - Page 18

• Manufacturer Part Number: MC7448VU1700LD
• Description: IC MPU RISC 32BIT 360-FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC7448VU1700LD

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 1.7GHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 360-FCCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Electrical and Thermal Characteristics
18
At recommended operating conditions. See
SYSCLK to output high impedance (all except TS, ARTRY,
SHD0, SHD1)
SYSCLK to TS high impedance after precharge
Maximum delay to ARTRY/SHD0/SHD1 precharge
SYSCLK to ARTRY/SHD0/SHD1 high impedance after
precharge
Notes:
1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input
2. The symbology used for timing specifications herein follows the pattern of t
3. t
4. According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low and precharged high
5. Guaranteed by design and not tested
6. According to the bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately following
7. According to the MPX bus protocol, SHD0 and SHD1 can be driven by multiple bus masters beginning two cycles after TS.
8. BMODE[0:1] and BVSEL[0:1] are mode select inputs. BMODE[0:1] are sampled before and after HRESET negation.
SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the signal
in question. All output timings assume a purely resistive 50-Ω load (see
the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
t
relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And t
SYSCLK(K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read as the time that the
input signal (I) went invalid (X) with respect to the rising clock edge (KH) (note the position of the reference and its state for
inputs) and output hold time can be read as the time from the rising edge (KH) until the output went invalid (OX).
SYSCLK to compute the actual time duration (in ns) of the parameter in question.
before returning to high impedance, as shown in
period. Since no master can assert TS on the following clock edge, there is no concern regarding contention with the
precharge. Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for precharge.The
high-impedance behavior is guaranteed by design.
AACK. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any master asserting it low
in the first clock following AACK will then go to high impedance for a fraction of a cycle, then negated for up to an entire cycle
(crossing a bus cycle boundary) before being three-stated again. The nominal precharge width for ARTRY is 1.0 t
that is, it should be high impedance as shown in
Output valid and output hold timing is tested for the signal asserted.The high-impedance behavior is guaranteed by design.
Timing is the same as ARTRY, that is, the signal is high impedance for a fraction of a cycle, then negated for up to an entire
cycle (crossing a bus cycle boundary) before being three-stated again. The nominal precharge width for SHD0 and SHD1 is
1.0 t
BVSEL[0:1] are sampled before HRESET negation. These parameters represent the input setup and hold times for each
sample. These values are guaranteed by design and not tested. BMODE[0:1] must remain stable after the second sample;
BVSEL[0:1] must remain stable after the first (and only) sample. See
(reference)(state)(signal)(state)
sysclk
SYSCLK
is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the period of
. The edges of the precharge vary depending on the programmed ratio of core to bus (PLL configurations).
Table 9. Processor Bus AC Timing Specifications
Parameter
MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4
for outputs. For example, t
Table
4.
Figure
Figure 6
IVKH
6. The nominal precharge width for TS is t
symbolizes the time input signals (I) reach the valid state (V)
before the first opportunity for another master to assert ARTRY.
Symbol
t
t
t
KHARPZ
KHTSPZ
t
KHARP
KHOZ
Figure 5
Figure
2
(signal)(state)(reference)(state)
for sample timing.
4). Input and output timings are measured at
All Speed Grades
Min
—
—
—
—
1
(continued)
KHOV
Max
1.8
1
1
2
symbolizes the time from
SYSCLK
Freescale Semiconductor
for inputs and
t
t
t
SYSCLK
SYSCLK
SYSCLK
, that is, one clock
Unit
ns
SYSCLK
3, 5, 6, 7
3, 5, 6, 7
Notes
3, 4, 5
5
;