MC7448VU1700LD Freescale Semiconductor, MC7448VU1700LD Datasheet - Page 53

• Manufacturer Part Number: MC7448VU1700LD
• Description: IC MPU RISC 32BIT 360-FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC7448VU1700LD

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 1.7GHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 360-FCCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Solving for T, the equation becomes:
9.7.5
The DFS feature in the MPC7448 adds the ability to divide the processor-to-system bus ratio by two or
four during normal functional operation. Divide-by-two mode is enabled by setting the HID1[DFS2] bit
in software or by asserting the DFS2 pin via hardware. The MPC7448 can be returned for full speed by
clearing HID1[DFS2] or negating DFS2. Similarly, divide-by-four mode is enabled by setting
HID1[DFS4] in software or by asserting the DFS4 pin. In all cases, the frequency change occurs in 1 clock
cycle and no idle waiting period is required to switch between modes. Note that asserting either DFS2 or
DFS4 overrides software control of DFS, and that asserting both DFS2 and DFS4 disables DFS
completely, including software control. Additional information regarding DFS can be found in the
MPC7450 RISC Microprocessor Family Reference Manual. Note that minimum core frequency
requirements must be observed when enabling DFS, and the resulting core frequency must meet the
requirements for f
9.7.5.1
Power consumption with DFS enabled can be approximated using the following formula:
Where:
The above is an approximation only. Power consumption with DFS enabled is not tested or guaranteed.
9.7.5.2
DFS is not available for all bus-to-core multipliers as configured by PLL_CFG[0:5] during hard reset. The
complete listing is shown in
particular PLL_CFG[0:5] setting. Should software or hardware attempt to transition to a multiplier that is
not supported, the device will remain at its current multiplier. For example, if a transition from
DFS-disabled to an unsupported divide-by-2 or divide-by-4 setting is attempted, the bus-to-core multiplier
will remain at the setting configured by the PLL_CFG[0:5] pins. In the case of an attempted transition from
a supported divide-by-2 mode to an unsupported divide-by-4 mode, the device will remain in divide-by-2
mode. In all cases, the HID1[PC0-5] bits will correctly reflect the current bus-to-core frequency multiplier.
Freescale Semiconductor
nT =
P
P
f
f = Core frequency prior to enabling DFS
P = Power consumption prior to enabling DFS (see
P
DFS
DFS
DFS
DS
= Deep sleep mode power consumption (see
= Power consumption with DFS enabled
= Core frequency with DFS enabled
=
Dynamic Frequency Switching (DFS)
Power Consumption with DFS Enabled
Bus-to-Core Multiplier Constraints with DFS
__________
1.986 × 10
f
___
DFS
f
V
H
core_DFS
– V
(P – P
L
MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4
–4
given in
Table
DS
) + P
16. Shaded cells represent DFS modes that are not available for a
Table
DS
8.
Table
Table
7)
7)
System Design Information
53