MC7448VU1700LD Freescale Semiconductor, MC7448VU1700LD Datasheet - Page 37

• Manufacturer Part Number: MC7448VU1700LD
• Description: IC MPU RISC 32BIT 360-FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC7448VU1700LD

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 1.7GHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 360-FCCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

9.1.2
Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference
emissions (EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise
magnitude in order to meet industry and government requirements. These clock sources intentionally add
long-term jitter in order to diffuse the EMI spectral content. The jitter specification given in
considers short-term (cycle-to-cycle) jitter only and the clock generator’s cycle-to-cycle output jitter
should meet the MPC7448 input cycle-to-cycle jitter requirement. Frequency modulation and spread are
separate concerns, and the MPC7448 is compatible with spread spectrum sources if the recommendations
listed in
It is imperative to note that the processor’s minimum and maximum SYSCLK, core, and VCO frequencies
must not be exceeded regardless of the type of clock source. Therefore, systems in which the processor is
operated at its maximum rated core or bus frequency should avoid violating the stated limits by using
down-spreading only.
9.2
The following sections provide detailed information regarding power supply design for the MPC7448.
9.2.1
The MPC7448 requires its power rails and clock to be applied in a specific sequence to ensure proper
device operation and to prevent device damage. The power sequencing requirements are as follows:
Additionally, the following requirements exist regarding the application of SYSCLK:
Freescale Semiconductor
•
•
•
•
AV
described in
OV
The voltage at the SYSCLK input must not exceed V
The voltage at the SYSCLK input must not exceed OV
overshoot/undershoot specifications in
Table 13
At recommended operating conditions. See
Power Supply Design and Sequencing
Frequency modulation
Frequency spread
Notes:
1. Guaranteed by design
2. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO
DD
DD
System Bus Clock (SYSCLK) and Spread Spectrum Sources
Power Supply Sequencing
frequencies, must meet the minimum and maximum specifications given in
must be delayed with respect to V
may ramp anytime before or after V
are observed.
Section 9.2.2, “PLL Power Supply Filtering”.
Table 13. Spread Spectrum Clock Source Recommendations
MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4
Parameter
Table
4.
Figure
DD
DD
by the RC time constant of the PLL filter circuit
2) or 0.3 V DC (see
and AV
Min
—
—
DD
DD
DD
until V
.
This time constant is nominally 100 µs.
by more 20% during transients (see
Max
1.0
50
DD
Table
has ramped to 0.9 V.
Table
8.
Unit
kHz
2) at any time.
%
System Design Information
Notes
1, 2
1
Table 8
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