MC7448VU1700LD Freescale Semiconductor, MC7448VU1700LD Datasheet - Page 6

• Manufacturer Part Number: MC7448VU1700LD
• Description: IC MPU RISC 32BIT 360-FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC7448VU1700LD

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 1.7GHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 360-FCCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Features
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Efficient data flow
— Although the VR/LSU interface is 128 bits, the L1/L2 bus interface allows up to 256 bits.
— The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs.
— The L2 cache is fully pipelined to provide 32 bytes per clock every other cycle to the L1 caches.
— As many as 16 out-of-order transactions can be present on the MPX bus.
— Store merging for multiple store misses to the same line. Only coherency action taken
— Three-entry finished store queue and five-entry completed store queue between the LSU and
— Separate additional queues for efficient buffering of outbound data (such as castouts and
Multiprocessing support features include the following:
— Hardware-enforced, MESI cache coherency protocols for data cache
— Load/store with reservation instruction pair for atomic memory references, semaphores, and
Power and thermal management
— Dynamic frequency switching (DFS) feature allows processor core frequency to be halved or
— The following three power-saving modes are available to the system:
— Instruction cache throttling provides control of instruction fetching to limit device temperature.
— A new temperature diode that can determine the temperature of the microprocessor
Performance monitor can be used to help debug system designs and improve software efficiency.
In-system testability and debugging features through JTAG boundary-scan capability
Testability
— LSSD scan design
— IEEE Std. 1149.1™ JTAG interface
(address-only) for store misses merged to all 32 bytes of a cache block (no data tenure needed).
the L1 data cache
write-through stores) from the L1 data cache and L2 cache
other multiprocessor operations
quartered through software to reduce power consumption.
– Nap—Instruction fetching is halted. Only the clocks for the time base, decrementer, and
– Sleep—Power consumption is further reduced by disabling bus snooping, leaving only the
– Deep sleep—When the part is in the sleep state, the system can disable the PLL. The system
JTAG logic remain running. The part goes into the doze state to snoop memory operations
on the bus and then back to nap using a QREQ/QACK processor-system handshake
protocol.
PLL in a locked and running state. All internal functional units are disabled.
can then disable the SYSCLK source for greater system power savings. Power-on reset
procedures for restarting and relocking the PLL must be followed upon exiting the deep
sleep state.
MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4
Freescale Semiconductor