MC7448VU1700LD Freescale Semiconductor, MC7448VU1700LD Datasheet - Page 35

• Manufacturer Part Number: MC7448VU1700LD
• Description: IC MPU RISC 32BIT 360-FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC7448VU1700LD

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 1.7GHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 360-FCCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

9
This section provides system and thermal design requirements and recommendations for successful
application of the MPC7448.
9.1
The following sections provide more detailed information regarding the clocking of the MPC7448.
9.1.1
The MPC7448 PLL is configured by the PLL_CFG[0:5] signals. For a given SYSCLK (bus) frequency,
the PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL
configuration for the MPC7448 is shown in
for a given SYSCLK frequency, result in core and/or VCO frequencies that do not comply with
When enabled, dynamic frequency switching (DFS) also affects the core frequency by halving or
quartering the bus-to-core multiplier; see
information. Note that when DFS is enabled the resulting core frequency must meet the adjusted minimum
core frequency requirements (f
for factory test only and should be tied low, and that the MPC7448 PLL configuration settings are
compatible with the MPC7447A PLL configuration settings when PLL_CFG[5] = 0.
Freescale Semiconductor
PLL_CFG[0:5]
010000
100000
101000
101100
100100
110100
010100
001000
000100
110000
011000
011110
011100
101010
100010
System Design Information
Clocks
PLL Configuration
Bus-to-Core
Multiplier
10.5x
2x
3x
4x
5.5x
6.5x
7.5x
8.5x
9.5x
10x
5x
6x
7x
8x
9x
6
6
6
Table 12. MPC7448 Microprocessor PLL Configuration Example
5
MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4
Core-to-VCO
Multiplier
core_DFS
1x
1x
1x
1x
1x
1x
1x
1x
1x
1x
1x
1x
1x
1x
1x
5
) described in
Example Core and VCO Frequency in MHz
MHz
Section 9.7.5, “Dynamic Frequency Switching (DFS),”
33.3
Table
MHz
50
12. In this example, shaded cells represent settings that,
Table
MHz
66.6
600
633
667
700
8. Note that the PLL_CFG[5] is currently used
Bus (SYSCLK) Frequency
MHz
600
638
675
712
750
938
75
MHz
623
664
706
747
789
830
872
83
1000
1050
MHz
100
600
650
700
750
800
850
900
950
System Design Information
1000
1064
1131
1197
1264
1333
1397
MHz
133
667
733
800
866
931
1002
1086
1169
1253
1336
1417
1500
1583
1667
MHz
167
667
835
919
Table
for more
1000
1100
1200
1300
1400
1500
1600
1700
MHz
200
600
800
8.
35