MC7448VU1700LD Freescale Semiconductor, MC7448VU1700LD Datasheet - Page 39

• Manufacturer Part Number: MC7448VU1700LD
• Description: IC MPU RISC 32BIT 360-FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC7448VU1700LD

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 1.7GHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 360-FCCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

There is no requirement regarding AV
within the RC time constant of the PLL filter circuit described in
Filtering”
9.2.2
The AV
ensure stability of the internal clock, the power supplied to the AV
noise in the 500-KHz to 10-MHz resonant frequency range of the PLL. The circuit shown in
using surface mount capacitors with minimum effective series inductance (ESL) is strongly recommended.
In addition to filtering noise from the AV
AV
The circuit should be placed as close as possible to the AV
circuits. It is often possible to route directly from the capacitors to the AV
of the device footprint.
Freescale Semiconductor
DD
SYSCLK
as described in
DD
OV
V
AV
(nominally 100 µs).
DD
power signal is provided on the MPC7448 to provide power to the clock generation PLL. To
PLL Power Supply Filtering
DD
DD
note also restrictions between SYSCLK and OV
limit imposed by OV
V
DD
Section 9.2.1, “Power Supply Sequencing.”
Figure 17. MPC7448 Power Down Sequencing Requirements
MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4
10 Ω
Figure 18. PLL Power Supply Filter Circuit
DD
if OV
DD
during power down, but it is recommended that AV
DD
DD
2.2 µF
ramps down first
input, it also provides the required delay between V
GND
Low ESL Surface Mount Capacitors
DD
limit imposed by V
2.2 µF
no restrictions between V
DD
0.9 V
pin to minimize noise coupled from nearby
0.9 V
no restrictions between V
DD
Section 9.2.2, “PLL Power Supply
AV
input signal should be filtered of any
DD
DD
DD
if V
pin, which is on the periphery
DD
DD
ramps down first
and OV
System Design Information
DD
and AV
DD
DD
Figure 18
DD
track V
DD
and
DD
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