MC7448VU1700LD Freescale Semiconductor, MC7448VU1700LD Datasheet - Page 36

• Manufacturer Part Number: MC7448VU1700LD
• Description: IC MPU RISC 32BIT 360-FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC7448VU1700LD

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 1.7GHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 360-FCCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

System Design Information
36
PLL_CFG[0:5]
Notes:
1. PLL_CFG[0:5] settings not listed are reserved.
2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled. However, the
4. In PLL-off mode, no clocking occurs inside the MPC7448 regardless of the SYSCLK input.
5. Applicable when DFS modes are disabled. These multipliers change when operating in a DFS mode. See
6. Bus-to-core multipliers less than 5x require that assertion of AACK be delayed by one or two bus cycles to allow the
frequencies which are not useful, not supported, or not tested for by the MPC7448; see
Specifications,” for valid SYSCLK, core, and VCO frequencies.
bus interface unit requires a 2x clock to function. Therefore, an additional signal, EXT_QUAL, must be driven at half the
frequency of SYSCLK and offset in phase to meet the required input setup t
will be that the processor bus frequency will be one-half SYSCLK, while the internal processor is clocked at SYSCLK
frequency. This mode is intended for factory use and emulator tool use only.
Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.
“Dynamic Frequency Switching
processor to generate a response to a snooped transaction. See the MPC7450 RISC Microprocessor Reference Manual for
more information.
100110
000000
101110
111110
010110
111000
110010
000110
110110
000010
001010
001110
010010
011010
111010
001100
111100
Bus-to-Core
Multiplier
Table 12. MPC7448 Microprocessor PLL Configuration Example (continued)
11.5x
12.5x
13.5x
11x
12x
13x
14x
15x
16x
17x
18x
20x
21x
24x
28x
PLL bypass
PLL off
5
MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4
Core-to-VCO
Multiplier
(DFS)” for more information.
1x
1x
1x
1x
1x
1x
1x
1x
1x
1x
1x
1x
1x
1x
1x
5
Example Core and VCO Frequency in MHz
MHz
33.3
600
667
700
800
933
PLL off, SYSCLK clocks core circuitry directly
1000
1050
1200
1400
MHz
600
625
650
675
700
750
800
850
900
50
PLL off, no core clocking occurs
1000
1066
1132
1200
1332
1399
1600
MHz
66.6
733
766
800
833
865
900
933
Bus (SYSCLK) Frequency
1013
1050
1125
1200
1275
1350
1500
1575
MHz
825
863
900
938
975
75
IVKH
and hold time t
1038
1079
1121
1162
1245
1328
1417
1500
1666
MHz
913
955
996
83
Section 5.2.1, “Clock AC
1100
1150
1200
1250
1300
1350
1400
1500
1600
1700
MHz
100
IXKH
Freescale Semiconductor
(see
1467
1533
1600
1667
MHz
133
Table
Section 9.7.5,
MHz
167
9). The result
MHz
200