MC7448VU1700LD Freescale Semiconductor, MC7448VU1700LD Datasheet - Page 55

• Manufacturer Part Number: MC7448VU1700LD
• Description: IC MPU RISC 32BIT 360-FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC7448VU1700LD

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 1.7GHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 360-FCCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

9.7.5.3
In many systems, enabling DFS can result in very low processor core frequencies. However, care must be
taken to ensure that the resulting processor core frequency is within the limits specified in
operation of the device is not guaranteed at core frequencies below the specified minimum f
10 Document Revision History
Table 17
Freescale Semiconductor
Revision
Notes:
1. DFS mode is not supported for this combination of DFS mode and PLL_CFG[0:5] setting. As a result, the processor
2. Though supported by the MPC7448 clock circuitry, multipliers of n.25x and n.75x cannot be expressed as valid PLL
3. Note that in the HID1 register of the MPC7448, the PC0, PC1, PC2, PC3, PC4, and PC5 bits are bits 15, 16, 17, 18,
4. Special considerations regarding snooped transactions must be observed for bus-to-core multipliers less than 5x.
Bus-to-Core Multiplier
4
3
configuration codes. As a result, the values displayed in HID1[PC0-PC5] are rounded down to the nearest valid PLL
configuration code. However, the actual bus-to-core multiplier is as stated in this table.
19, and 14 (respectively). See the MPC7450 RISC Microprocessor Reference Manual for more information.
See the MPC7450 RISC Microprocessor Reference Manual for more information.
will ignore these settings and remain at the previous multiplier, as reflected by the HID1[PC0-PC5] bits.
Configured by
PLL_CFG[0:5]
(see
provides a revision history for this hardware specification.
10/2006
3/2007
Date
Table
DFS mode disabled
24x
28x
Minimum Core Frequency Requirements with DFS
12)
Table
Section 9.7, “Power and Thermal Management
Table
Table
frequency, and footnotes 1 and 2.
Table
Table 19
19: Added 800 MHz processor frequency.
18,
19: Added 600 processor frequency, additional product codes, date codes for 1400 processor
20: Added PPC product code and footnote 1.
MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4
HID1[PC0-5]
Table 16. Valid Divide Ratio Configurations (continued)
and
Table
011010
111010
Table
20, and
Table 17. Document Revision History
20: Added Revision D information for 1267 processor frequency.
3
Table
DFS divide-by-2 mode enabled
(HID1[DFS2] = 1 or DFS2 = 0)
Bus-to-Core
Multiplier
19: Added Revision D PVR.
12x
14x
Substantive Change(s)
HID1[PC0-5]
Information”: Updated contact information.
101110
110010
3
DFS divide-by-4 mode enabled
(HID1[DFS4] = 1 or DFS4 = 0)
Bus-to-Core
Multiplier
6x
7x
Document Revision History
HID1[PC0-5]
Table
110100
001000
core
8. Proper
.
3
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