MC7448VU1700LD Freescale Semiconductor, MC7448VU1700LD Datasheet - Page 4

• Manufacturer Part Number: MC7448VU1700LD
• Description: IC MPU RISC 32BIT 360-FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC7448VU1700LD

• Processor Type: MPC74xx PowerPC 32-Bit
• Speed: 1.7GHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 360-FCCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Features
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— Four vector units and 32-entry vector register file (VRs)
— Three-stage load/store unit (LSU)
Three issue queues, FIQ, VIQ, and GIQ, can accept as many as one, two, and three instructions,
respectively, in a cycle. Instruction dispatch requires the following:
— Instructions can only be dispatched from the three lowest IQ entries—IQ0, IQ1, and IQ2.
— A maximum of three instructions can be dispatched to the issue queues per clock cycle.
— Space must be available in the CQ for an instruction to dispatch (this includes instructions that
Rename buffers
— 16 GPR rename buffers
— 16 FPR rename buffers
— 16 VR rename buffers
Dispatch unit
— Decode/dispatch stage fully decodes each instruction
Completion unit
— Retires an instruction from the 16-entry completion queue (CQ) when all instructions ahead of
— Guarantees sequential programming model (precise exception model)
– Vector permute unit (VPU)
– Vector integer unit 1 (VIU1) handles short-latency AltiVec™ integer instructions, such as
– Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as
– Vector floating-point unit (VFPU)
– Supports integer, floating-point, and vector instruction load/store traffic
– Four-entry vector touch queue (VTQ) supports all four architected AltiVec data stream
– Three-cycle GPR and AltiVec load latency (byte, half word, word, vector) with one-cycle
– Four-cycle FPR load latency (single, double) with one-cycle throughput
– No additional delay for misaligned access within double-word boundary
– A dedicated adder calculates effective addresses (EAs).
– Supports store gathering
– Performs alignment, normalization, and precision conversion for floating-point data
– Executes cache control and TLB instructions
– Performs alignment, zero padding, and sign extension for integer data
– Supports hits under misses (multiple outstanding misses)
– Supports both big- and little-endian modes, including misaligned little-endian accesses
are assigned a space in the CQ but not in an issue queue).
it have been completed, the instruction has finished executing, and no exceptions are pending
vector add instructions (for example, vaddsbs, vaddshs, and vaddsws).
vector multiply add instructions (for example, vmhaddshs, vmhraddshs, and
vmladduhm).
operations
throughput
MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4
Freescale Semiconductor