PIC18F2431-I/SP Microchip Technology Inc., PIC18F2431-I/SP Datasheet - Page 108

• Manufacturer Part Number: PIC18F2431-I/SP
• Description: Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2431-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2331/2431/4331/4431
9.6
External interrupts on the RC3/INT0, RC4/INT1 and
RC5/INT2 pins are edge triggered: either rising, if the
corresponding INTEDGx bit is set in the INTCON2
register, or falling, if the INTEDGx bit is clear. When a
valid edge appears on the RC3/INT0 pin, the
corresponding flag bit INTxF is set. This interrupt can
be disabled by clearing the corresponding enable bit
INTxE. Flag bit INTxF must be cleared in software in
the interrupt service routine before re-enabling the
interrupt. All external interrupts (INT0, INT1 and INT2)
can wake-up the processor from the power-managed
modes, if bit INTxE was set prior to going into power-
managed modes. If the global interrupt enable bit GIE
is set, the processor will branch to the interrupt vector
following wake-up.
Interrupt priority for INT1 and INT2 is determined by the
value contained in the interrupt priority bits, INT1IP
(INTCON3<6>) and INT2IP (INTCON3<7>). There is
no priority bit associated with INT0. It is always a high
priority interrupt source.
EXAMPLE 9-1:
DS39616B-page 106
MOVWF
MOVFF
MOVFF
;
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
INTn Pin Interrupts
W_TEMP
STATUS,STATUS_TEMP
BSR,BSR_TEMP
BSR_TEMP,BSR
W_TEMP, W
STATUS_TEMP, STATUS
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
; Restore BSR
; Restore WREG
; Restore STATUS
Preliminary
9.7
In 8-bit mode (which is the default), an overflow
(FFh
TMR0IF. In 16-bit mode, an overflow (FFFFh
in the TMR0H:TMR0L registers will set flag bit TMR0IF.
The interrupt can be enabled/disabled by setting/clear-
ing enable bit TMR0IE (INTCON<5>). Interrupt priority
for Timer0 is determined by the value contained in the
interrupt priority bit TMR0IP (INTCON2<2>). See
Section 11.0 “Timer0 Module” for further details.
9.8
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
9.9
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, Status and BSR
registers are saved on the fast return stack. If a fast
return from interrupt is not used (See Section 5.3
“Fast Register Stack”), the user may need to save the
WREG, Status and BSR registers on entry to the
interrupt service routine. Depending on the user’s
application, other registers may also need to be saved.
Example 9-1 saves and restores the WREG, Status
and BSR registers during an interrupt service routine.
00h) in the TMR0 register will set flag bit
TMR0 Interrupt
PORTB Interrupt-on-Change
Context Saving During Interrupts
 2003 Microchip Technology Inc.
0000h)