PIC18F2431-I/SP Microchip Technology Inc., PIC18F2431-I/SP Datasheet - Page 169

• Manufacturer Part Number: PIC18F2431-I/SP
• Description: Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2431-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

16.1.5
The following is a summary of functional operation
upon entering any of the Input Capture modes:
1.
2.
 2003 Microchip Technology Inc.
After the module is configured for one of the
capture modes by setting the Mode Select bits
(CAPxM3:CAPxM0), the first detected edge
captures Timer5 value and stores it in the CAPx-
BUF register. The timer is then reset (depending
on the setting of CAPxREN bit) and starts to
increment according to its settings, see
Figure 16-4, Figure 16-5 and Figure 16-6.
On all edges, the capture logic performs the fol-
lowing:
a)
b)
c)
d)
e)
f)
Input Capture mode is decoded and the
active edge is identified
The CAPxREN bit is checked to determine
whether Timer5 is reset or not.
On every active edge, the Timer5 value is
recorded in the input capture buffer (CAPx-
BUF).
Reset Timer5 after capturing the value of
the timer when CAPxREN bit is enabled.
Timer5 is reset on every active capture
edge in this case.
On all continuing capture edge events
repeat steps 1 through 4 until the Opera-
tional mode is terminated either by user
firmware, POR or BOR.
The timer value is not affected when switch-
ing into and out of various input capture
modes.
ENTERING INPUT CAPTURE MODE
AND CAPTURE TIMING
PIC18F2331/2431/4331/4431
Preliminary
16.1.6
Every Input Capture trigger can optionally reset
(TMR5). Capture Reset Enable bit, CAPxREN, gates
the automatic Reset of the time base of the capture
event with this enable Reset signal. All capture events
reset the selected timer when CAPxREN is set. Resets
are disabled when CAPxREN is cleared (see
Figure 16-4, Figure 16-5 and Figure 16-6).
16.1.7
There are four operating modes for which the IC
module can generate an interrupt and set one of the
Interrupt Capture flag bits (IC1IF, IC2QEIF or
IC3DRIF). The interrupt flag that is set depends on the
channel in which the event occurs. The modes are:
• Edge capture (CAPxM3:CAPxM0 = 0001, 0010,
• Period measurement event
• Pulse width measurement event
• State change event (CAPxM3:CAPxM0 = 1000)
The timing of interrupt and special trigger events is
shown in Figure 16-7. Any active edge is detected on
the rising edge of Q2 and propagated on the rising
edge of Q4 rising edge. If an active edge happens to
occur any later than this (on the falling edge of Q2, for
example), then it will be recognized on the next Q2
rising edge.
Note:
0011 or 0100)
(CAPxM3:CAPxM0 = 0101)
(CAPxM3:CAPxM0 = 0110 or 0111)
Note:
TIMER5 RESET
The CAPxREN bit has no effect in Pulse
Width Measurement mode.
IC INTERRUPTS
The special event trigger is generated only
in the Special Event Trigger mode on
CAP1 input (CAP1M2:CAP1M0> = 1110
and 1111). IC1IF interrupt is not set in this
mode.
DS39616B-page 167