PIC18F2431-I/SP Microchip Technology Inc., PIC18F2431-I/SP Datasheet - Page 33

• Manufacturer Part Number: PIC18F2431-I/SP
• Description: Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2431-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

3.0
The PIC18F2331/2431/4331/4431 devices offer a total
of six operating modes for more efficient power
management (see Table 3-1). These operating modes
provide a variety of options for selective power
conservation in applications where resources may be
limited (i.e., battery-powered devices).
There are three categories of power-managed modes:
• Sleep mode
• Idle modes
• Run modes
These categories define which portions of the device
are clocked and sometimes, what speed. The run and
idle modes may use any of the three available clock
sources (Primary, Secondary or INTOSC multiplexer);
the Sleep mode does not use a clock source.
The clock switching feature offered in other PIC18
devices (i.e., using the Timer1 oscillator in place of the
primary oscillator), and the Sleep mode offered by all
PICmicro
stopped) are both offered in the PIC18F2331/2431/
4331/4431 devices (SEC_RUN and Sleep modes,
respectively). However, additional power-managed
modes are available that allow the user greater flexibil-
ity in determining what portions of the device are oper-
ating. The power-managed modes are event driven;
that is, some specific event must occur for the device to
enter or (more particularly) exit these operating modes.
For PIC18F2331/2431/4331/4431 devices, the power-
managed modes are invoked by using the existing
SLEEP instruction. All modes exit to PRI_RUN mode
when triggered by an interrupt, a Reset or a WDT time-
out (PRI_RUN mode is the normal full power execution
mode; the CPU and peripherals are clocked by the pri-
mary oscillator source). In addition, power-managed
run modes may also exit to Sleep mode or their
corresponding idle mode.
TABLE 3-1:
 2003 Microchip Technology Inc.
Sleep
PRI_RUN
SEC_RUN
RC_RUN
PRI_IDLE
SEC_IDLE
RC_IDLE
Note 1:
Mode
POWER-MANAGED MODES
®
Includes INTOSC and INTOSC postscaler, as well as the INTRC source.
devices (where all system clocks are
IDLEN
<7>
POWER-MANAGED MODES
0
0
0
0
1
1
1
OSCCON bits
SCS1:SCS0
<1:0>
00
00
01
1x
00
01
1x
Clocked
Clocked
Clocked
CPU
Off
Off
Off
Off
Module Clocking
PIC18F2331/2431/4331/4431
Preliminary
Peripherals
Clocked
Clocked
Clocked
Clocked
Clocked
Clocked
Off
3.1
Selecting a power-managed mode requires deciding if
the CPU is to be clocked or not, and selecting a clock
source. The IDLEN bit controls CPU clocking, while the
SC1:SCS0 bits select a clock source. The individual
modes, bit settings, clock sources and affected
modules are summarized in Table 3-1.
3.1.1
The clock source is selected by setting the SCS bits of
the OSCCON register. Three clock sources are avail-
able for use in power-managed idle modes: the primary
clock (as configured in Configuration Register 1H), the
secondary clock (Timer1 oscillator), and the internal
oscillator block. The secondary and internal oscillator
block sources are available for the power-managed
modes (PRI_RUN mode is the normal full power exe-
cution mode; the CPU and peripherals are clocked by
the primary oscillator source).
None – All clocks are disabled
Primary – LP, XT, HS, HSPLL, RC, EC, INTRC
This is the normal full power execution mode.
Secondary – Timer1 Oscillator
Internal Oscillator Block
Primary – LP, XT, HS, HSPLL, RC, EC
Secondary – Timer1 Oscillator
Internal Oscillator Block
Selecting Power-Managed Modes
Available Clock and Oscillator Source
CLOCK SOURCES
(1)
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DS39616B-page 31
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