PIC18F2431-I/SP Microchip Technology Inc., PIC18F2431-I/SP Datasheet - Page 215

• Manufacturer Part Number: PIC18F2431-I/SP
• Description: Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2431-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

REGISTER 18-2:
 2003 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3-0
SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word
0 = No collision
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is received, while the SSPBUF register is still holding the previous data. In case
0 = No overflow
In I
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV
0 = No overflow
SSPEN: Synchronous Serial Port Enable bit
In SPI mode:
1 = Enables serial port and configures SCK, SDO and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In both modes, when enabled, these pins must be properly configured as input or output.
CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level (Microwire
0 = Idle state for clock is a low level (Microwire
In I
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = F
0001 = SPI Master mode, clock = F
0010 = SPI Master mode, clock = F
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0110 = I
0111 = I
1011 = I
1110 = I
1111 = I
bit 7
Legend:
R = Readable bit
- n = Value at POR reset
WCOL
R/W-0
2
2
2
C mode:
C mode:
C mode:
(must be cleared in software)
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user
must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In
Master mode, the overflow bit is not set since each new reception (and transmission) is
initiated by writing to the SSPBUF register.
is a “don’t care” in Transmit mode. SSPOV must be cleared in software in either mode.
2
2
2
2
2
C Slave mode, 7-bit address
C Slave mode, 10-bit address
C Firmware Controlled Master mode (slave Idle)
C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
SSPOV
R/W-0
PIC18F2331/2431/4331/4431
SSPEN
R/W-0
Preliminary
W = Writable bit
‘1’ = Bit is set
OSC
OSC
OSC
R/W-0
CKP
/4
/16
/64
®
®
alternate)
default)
SSPM3
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
SSPM2
R/W-0
x = Bit is unknown
SSPM1
R/W-0
DS39616B-page 213
SSPM0
R/W-0
bit 0