PIC18F2431-I/SP Microchip Technology Inc., PIC18F2431-I/SP Datasheet - Page 68

• Manufacturer Part Number: PIC18F2431-I/SP
• Description: Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2431-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2331/2431/4331/4431
TABLE 5-2:
DS39616B-page 66
TOSU
TOSH
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
POSTINC0
POSTDEC0
PREINC0
PLUSW0
FSR0H
FSR0L
WREG
INDF1
POSTINC1
POSTDEC1
PREINC1
PLUSW1
FSR1H
FSR1L
BSR
INDF2
POSTINC2
POSTDEC2
PREINC2
PLUSW2
FSR2H
FSR2L
STATUS
TMR0H
TMR0L
T0CON
Legend:
Note
File Name
1:
2:
3:
4:
5:
6:
x
RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only, and read
‘0’ in all other oscillator modes.
RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
Bit 21 of the PC is only available in Test mode and serial programming modes.
If PBADEN = 0, PORTB<4:0> are configured as digital input and read unknown, and if PBADEN = 1, PORTB<4:0> are configured as
analog input and read ‘0’ following a Reset.
These registers and/or bits are not implemented on the PIC18F2X31 devices, and read as ‘0’.
The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RE3 reads ‘0’. This bit is read-only.
Top-of-Stack High Byte (TOS<15:8>)
Top-of-Stack Low Byte (TOS<7:0>)
Holding register for PC<15:8>
PC Low Byte (PC<7:0>)
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product register High Byte
Product register Low Byte
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 offset by W (not a physical register)
Indirect Data Memory Address Pointer 0 Low Byte
Working register
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 offset by W (not a physical register)
Indirect Data Memory Address Pointer 1 Low Byte
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 offset by W (not a physical register)
Indirect Data Memory Address Pointer 2 Low Byte
Timer0 register High Byte
Timer0 register Low Byte
GIE/GIEH
= unknown,
TMR0ON
STKFUL
INT2P
RBPU
Bit 7
—
—
—
—
—
—
—
—
REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431)
u
PEIE/GIEL
INTEDG0
STKUNF
T016BIT
= unchanged, – = unimplemented,
INT1P
Bit 6
—
—
—
—
—
—
—
—
INTEDG1
TMR0IE
bit 21
bit 21
Bit 5
—
—
—
—
—
—
—
—
—
(3)
(3)
Top-of-Stack Upper Byte (TOS<20:16>)
Return Stack Pointer
Holding register for PC<20:16>
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
INTEDG2
INT0IE
INT2IE
Bit 4
—
—
—
—
—
N
Preliminary
q
= value depends on condition
Indirect Data Memory Address Pointer 0 High
Indirect Data Memory Address Pointer 1 High
Bank Select Register
Indirect Data Memory Address Pointer 2 High
INT1IE
T0PS3
Bit 3
RBIE
OV
—
TMR0IP
TMR0IF
T0PS2
Bit 2
—
Z
INT2IF
T0PS1
INT0F
Bit 1
DC
—
 2003 Microchip Technology Inc.
INT1IF
T0PS0
RBIP
Bit 0
RBIF
C
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 -1-1
11-0 0-00
---- 0000
xxxx xxxx
xxxx xxxx
---- 0000
xxxx xxxx
---- 0000
---- 0000
xxxx xxxx
---x xxxx
0000 0000
xxxx xxxx
11-- 1111
POR, BOR
Value on
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Details on
49, 135
49, 135
49, 133
48, 58
48, 58
48, 58
48, 59
48, 60
48, 60
48, 60
48, 78
48, 78
48, 78
48, 78
48, 89
48, 89
48, 93
48, 94
48, 95
48, 71
48, 71
48, 71
48, 71
48, 71
48, 71
48, 71
48, 71
48, 71
48, 71
48, 71
48, 71
49, 71
49, 71
49, 70
49, 71
49, 71
49, 71
49, 71
49, 71
49, 71
49, 71
49, 73
page:
48