PIC18F2431-I/SP Microchip Technology Inc., PIC18F2431-I/SP Datasheet - Page 175

• Manufacturer Part Number: PIC18F2431-I/SP
• Description: Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2431-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

16.2.3.3
The position counter will continue to increment or dec-
rement until one of the following events takes place.
The type of event and the direction of rotation when it
happens determines if a register reset or update
occurs.
1.
2.
The value of the position counter is not affected during
QEI mode changes, nor when the QEI is disabled
altogether.
 2003 Microchip Technology Inc.
An index pulse is detected on the INDX input
(QEIM2:QEIM0 = 001).
If the encoder is traveling in the forward direc-
tion, POSCNT is reset (00h) on the next clock
edge after the index marker, INDX, has been
detected. The position counter resets on the
QEA or QEB edge once the INDX rising edge
has been detected.
If the encoder is traveling in the reverse direc-
tion, the value in the MAXCNT register is loaded
into POSCNT on the next quadrature pulse
edge (QEA or QEB) after the falling edge on
INDX has been detected.
A POSTCNT/MAXCNT period match occurs
(QEIM2:QEIM0 = 010).
If the encoder is traveling in the forward direc-
tion, POSCNT is reset (00h) on the next clock
edge when POSCNT = MAXCNT. An interrupt
event is triggered on the next T
(see Figure 16-10)
If the encoder is traveling in the reverse
direction and the value of POSCNT reaches
00h, POSCNT is loaded with the contents of
MAXCNT register on the next clock edge. An
interrupt event is triggered on the next T
the load operation (see Figure 16-10).
Reset and Update Events
CY
after the reset
CY
PIC18F2331/2431/4331/4431
after
Preliminary
16.2.4
The position counter interrupt occurs, and the interrupt
flag (IC2QEIF) is set, based on the following events:
• A POSCNT/MAXCNT period match event
• A POSCNT rollover (FFFFh to 0000h) in Period
• An index pulse detected on INDX.
The interrupt timing diagrams for IC2QEIF are shown in
Figure 16-10 and Figure 16-11.
When the direction has changed, the direction change
Interrupt flag (IC3DRIF) is set on the following T
clock (see Figure 16-10).
If the position counter rolls over in Index mode, the
ERROR bit will be set.
16.2.5
The quadrature input signals, QEA and QEB, may vary
in quadrature frequency. The minimum quadrature
input period T
The position count rate, F
the rotor’s RPM, line count D and QEI Update mode (x2
vs. x4); that is,
The maximum position count rate (i.e., 4x QEI
Update mode, D = 1024) with F
to 2.5 MHz, which corresponds to F
Figure 16-9 shows QEA and QEB quadrature inputs
timing when sampled by the noise filter.
(QEIM2:QEIM0 = 010 or 110)
mode only (QEIM2:QEIM0 = 010 or 110)
Note:
QEI INTERRUPTS
QEI SAMPLE TIMING
The number of incremental lines in the
position encoder is typically set at
D = 1024 and the QEI Update mode = x4.
QEI
is 16T
F
POS
CY
=
POS
.
4D RPM
------------------------
, is directly proportional to
60
CY
= 10 MIPS is equal
DS39616B-page 173
QEI
of 625 kHz.
CY