PIC18F2431-I/SP Microchip Technology Inc., PIC18F2431-I/SP Datasheet - Page 260

• Manufacturer Part Number: PIC18F2431-I/SP
• Description: Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2431-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2331/2431/4331/4431
20.9.1
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16-bits wide.
The A/D module gives the flexibility to left- or right-
justify the 10-bit result in the 16-bit result register. The
FIGURE 20-5:
EQUATION 20-3:
DS39616B-page 258
Simultaneous Mode:
Sequential Mode:
T = T
T = (T
ACQ
ACQ
A/D RESULT REGISTER
)
+ (T
A
7
+ (T
CON
0000 00
ADRESH
CON
)
A
A/D RESULT JUSTIFICATION
CONVERSION TIME FOR MULTICHANNEL MODES
)
+ (T
Right Justified
A
+ [(T
2 1 0 7
CON
ADFM = 1
ACQ
)
B
+ T
)
B
10-bit Result
ADRESL
- 12T
ACQ
+ (T
AD
] + (T
CON
0
CON
)
C
Preliminary
+ (T
10-bit Result
)
B
+ [(T
CON
)
ACQ
D
A/D Format Select bit (ADFM) controls this justification.
Figure 20-5 shows the operation of the A/D result
justification. The extra bits are loaded with ‘0’s. When
an A/D result will not overwrite these locations (A/D
disable), these registers may be used as two general
purpose 8-bit registers.
)
C
- 12T
7
AD
ADRESH
] + (T
10-bit Result
CON
ADFM = 0
Left Justified
)
C
0 7 6 5
+ [(T
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ACQ
ADRESL
0000 00
)
D
- 12T
AD
0
] + (T
CON
)
D