PIC18F2431-I/SP Microchip Technology Inc., PIC18F2431-I/SP Datasheet - Page 207

• Manufacturer Part Number: PIC18F2431-I/SP
• Description: Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2431-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

17.11 PWM Output and Polarity Control
There are three device configuration bits associated
with the PWM module that provide PWM output pin
control defined in CONFIG3L configuration register.
• HPOL configuration bit
• LPOL configuration bit
• PWMPIN configuration bit
These three configuration bits work in conjunction with
the three PWM enable bits (PWMEN2:PWMEN0) in the
PWMCON0 register. The configuration bits and PWM
enable bits ensure that the PWM pins are in the correct
states after a device Reset occurs.
FIGURE 17-23:
17.11.2
The polarity of the PWM I/O pins is set during device
programming via the HPOL and LPOL configuration
bits in the CONFIG3L device configuration register.
The HPOL configuration bit sets the output polarity for
the high-side PWM outputs, PWM1, PWM3, PWM5
and PWM7. The polarity is active-high when HPOL is
cleared (= 0), and active-low when it is set (= 1).
 2003 Microchip Technology Inc.
Note:
I/O pin has protection diodes to V
OUTPUT POLARITY CONTROL
PWM signal from
module
WR PORT
WR TRIS
PWM Pin Enable
Data Bus
RD TRIS
RD PORT
PWM I/O PIN BLOCK DIAGRAM
Data Latch
TRIS Latch
D
CK
D
CK
DD
and V
PIC18F2331/2431/4331/4431
Q
Q
Q
Q
SS
Preliminary
. PWM polarity selection logic not shown for clarity.
1
0
17.11.1
The PWMEN2:PWMEN0 control bits enable each
PWM output pin as required in the application.
All PWM I/O pins are general purpose I/O. When a pair
of pins are enabled for PWM output, the PORT and
TRIS registers controlling the pin are disabled. Refer to
Figure 17-23 for details.
The LPOL configuration bit sets the output polarity for
the low-side PWM outputs, PWM0, PWM2, PWM4 and
PWM6. As with HPOL, they are active-high when LPOL
is cleared, and active-low when set.
All output signals generated by the PWM module are
referenced to the polarity control bits, including those
generated by fault inputs or manual override (see
Section 17.10 “PWM Output Override”).
The default polarity configuration bits have the PWM
I/O pins in active-high output polarity.
Q
EN
D
OUTPUT PIN CONTROL
V
V
P
N
DD
SS
TTL or
Schmitt
Trigger
I/O Pin
DS39616B-page 205