PIC18F2431-I/SP Microchip Technology Inc., PIC18F2431-I/SP Datasheet - Page 236

• Manufacturer Part Number: PIC18F2431-I/SP
• Description: Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2431-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2331/2431/4331/4431
To set up an Asynchronous Transmission:
1.
2.
3.
FIGURE 19-6:
TABLE 19-6:
DS39616B-page 234
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCTL
SPBRGH
SPBRG
Legend:
Name
Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH (see Section 19.2 “USART Baud
Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, set enable bit TXIE.
Note:
RX (pin)
Rcv Shift
Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
x = unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for Asynchronous Reception.
USART Receive Register
Baud Rate Generator Register, High Byte
Baud Rate Generator Register, Low Byte
GIE/GIEH
SPEN
CSRC
Bit 7
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after
the third word, causing the OERR (overrun) bit to be set.
—
—
—
—
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Start
ASYNCHRONOUS RECEPTION
bit
PEIE/GIEL
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
bit0
bit1
TMR0IE
SREN
TXEN
RCIE
RCIP
RCIF
Bit 5
—
bit7/8
INT0IE
CREN
SYNC
SCKP
TXIE
TXIP
Bit 4
TXIF
Preliminary
Stop
bit
ADDEN
SENDB
BRG16
Word 1
RCREG
RBIE
Bit 3
Start
—
—
—
bit
bit0
TMR0IF
CCP1IF TMR2IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
4.
5.
6.
7.
If using interrupts, ensure that the GIE and PEIE bits in
the INTCON register (INTCON<7:6>) are set.
BRGH
FERR
Bit 2
—
If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Load data to the TXREG register (starts
transmission).
INT0IF
OERR
TRMT
WUE
Bit 1
bit7/8
Word 2
RCREG
Stop
bit
TMR1IF
ABDEN
RX9D
TX9D
RBIF
Bit 0
Start
 2003 Microchip Technology Inc.
bit
0000 000x
-000 -000
-000 -000
-111 -111
0000 -00x
0000 0000
0000 0010
-1-1 0-00
0000 0000
0000 0000
POR, BOR
Value on
bit7/8
Stop
0000 000u
-000 -000
-000 -000
-111 -111
0000 -00x
0000 0000
0000 0010
-1-1 0-00
0000 0000
0000 0000
bit
Value on
all other
Resets