PIC18F2431-I/SP Microchip Technology Inc., PIC18F2431-I/SP Datasheet - Page 281

• Manufacturer Part Number: PIC18F2431-I/SP
• Description: Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2431-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 22-2:
22.3
The Two-Speed Start-up feature helps to minimize the
latency period from oscillator start-up to code execution
by allowing the microcontroller to use the INTRC oscil-
lator as a clock source until the primary clock source is
available. It is enabled by setting the IESO bit in
Configuration Register 1H (CONFIG1H<7>).
Two-Speed Start-up is available only if the primary
Oscillator mode is LP, XT, HS or HSPLL (crystal-based
modes). Other sources do not require a OST start-up
delay; for these, Two-Speed Start-up is disabled.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the inter-
nal oscillator block as the clock source, following the
time-out of the Power-up Timer after a POR Reset is
enabled. This allows almost immediate code execu-
tion, while the primary oscillator starts and the OST is
running. Once the OST times out, the device automat-
ically switches to PRI_RUN mode.
Because the OSCCON register is cleared on Reset
events, the INTOSC (or postscaler) clock source is not
initially available after a Reset event; the INTRC clock
is used directly at its base frequency. To use a higher
clock speed on wake-up, the INTOSC or postscaler
clock sources can be selected to provide a higher clock
speed by setting bits IFRC2:IFRC0 immediately after
Reset. For wake-ups from Sleep, the INTOSC or
postscaler clock sources can be selected by setting
IFRC2:IFRC0 prior to entering Sleep mode.
In all other power-managed modes, Two-Speed Start-
up is not used. The device will be clocked by the cur-
rently selected clock source until the primary clock
source becomes available. The setting of the IESO bit
is ignored.
 2003 Microchip Technology Inc.
CONFIG2H
RCON
WDTCON
Legend: Shaded cells are not used by the Watchdog Timer.
Name
Two-Speed Start-up
SUMMARY OF WATCHDOG TIMER REGISTERS
WDTW
IPEN
Bit 7
—
Bit 6
—
—
—
WINEN
PIC18F2331/2431/4331/4431
Bit 5
—
—
Preliminary
WDTPS3
Bit 4
RI
—
22.3.1
While using the INTRC oscillator in Two-Speed Start-
up, the device still obeys the normal command
sequences for entering power-managed modes,
including
Section 3.1.3 “Multiple Sleep Commands”). In prac-
tice, this means that user code can change the
SCS1:SCS0 bit settings and issue SLEEP commands
before the OST times out. This would allow an applica-
tion to briefly wake-up, perform routine “housekeeping”
tasks and return to Sleep before the device starts to
operate from the primary oscillator.
User code can also check if the primary clock source is
currently providing the system clocking by checking the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the system clock.
Otherwise, the internal oscillator block is providing the
clock during wake-up from Reset or Sleep mode.
WDTPS2
Bit 3
TO
—
SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
serial
WDTPS2
Bit 2
SLEEP
PD
—
instructions
WDTPS0
Bit 1
POR
—
DS39616B-page 279
SWDTEN
WDTEN
(refer
Bit 0
BOR
to