SAF7849HL/M295,557 NXP Semiconductors, SAF7849HL/M295,557 Datasheet
SAF7849HL/M295,557
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SAF7849HL/M295,557 Summary of contents
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SAF784x One chip CD audio device with integrated MP3/WMA decoder Rev. 02 — 9 May 2008 1. General description The SAF784x is a single-chip solution CD audio decoder with on-chip MP3 and WMA decoding, digital servo, audio DAC, sample-rate converter, ...
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... NXP Semiconductors I Two additional analog audio inputs (AUX_L, AUX_R) to allow the ARM microprocessor access to external audio signals (e.g. tuner); allows audio algorithms (e.g. bass boost performed on external audio signals I Real-time clock operated from separate 32 kHz crystal; allows low-power Standby mode with real-time clock still operational ...
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... NXP Semiconductors I This product has been qualified in accordance with AEC-Q100 2.2 Formats Reads the following CD-decode formats I CD-R I CD-RW I CD- Red Book; IEC 60908 ) I CD-ROM (Mode 1 and Mode 2) I CD-MP3 I CD-WMA I Video CD I SACD (CD layer only) I Support 80 minute to 100 minute CD playback ...
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... NXP Semiconductors 4. Block diagram CHANNEL DECODER DIGITAL DECODER MOTOR CONTROL CHANNEL CLOCK CONTROL SERVO DIGITAL SERVO GENERAL PURPOSE ADC PROCESSOR CLOCK ANALOG ANALOG LASER PLL DRIVER Fig 1. SAF784x top level block diagram SAF784X_2 Product data sheet One chip CD audio device with integrated MP3/WMA decoder ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. 5.2 Pin description Table 2. Pin description All digital inputs and bidirectional pins are 5 V tolerant. Symbol Pin SL_SIN 1 COS/GPIO31 2 LPOWER 3 LASER 4 MONITOR 5 VSSA1 6 HF_MON 7 VDDA1 AUX_L 15 AUX_R 16 VDDA2 17 OPU_REF_OUT 18 VSSA2 19 OSCOUT 20 OSCIN 21 VDDA3 22 SAF784X_2 ...
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... NXP Semiconductors Table 2. Pin description …continued All digital inputs and bidirectional pins are 5 V tolerant. Symbol Pin DAC_LP 23 DAC_LN 24 DAC_VREF 25 DAC_RN 26 DAC_RP 27 DAC_FGND 28 VSSA3 29 OSC_32K_IN 30 OSC_32K_OUT 31 VDDD1 32 A_IN1/GPIO0 33 A_IN2/GPIO1 34 A_IN3/GPIO2 35 A_IN4/GPIO3 36 VSSD1 37 TX/GPIO4 38 RX/GPIO5 39 TX2/GPIO6 40 DM_ADDR_0 41 RX2/GPIO7 42 DM_ADDR_1 43 SDA 44 DM_ADDR_2 45 SCL ...
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... NXP Semiconductors Table 2. Pin description …continued All digital inputs and bidirectional pins are 5 V tolerant. Symbol Pin GPIO12 63 DM_ADDR_10 64 GPIO13 65 DM_ADDR_11 66 GPIO14 67 DM_ADDR_12 68 GPIO15 69 DM_ADDR_13 70 SDI/GPIO16 71 DM_ADDR_14 72 WLCI/GPIO17 73 DM_ADDR_15 74 SCLI/GPIO18 75 VSSD2 76 VDDD2 77 DM_ADDR_16 78 T1/GPIO19 79 DM_ADDR_17 80 T2/GPIO20 81 DM_ADDR_18 82 T3/GPIO21 83 DM_ADDR_19 84 PWM1/CAP1/GPIO22 85 DM_ADDR_20 ...
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... NXP Semiconductors Table 2. Pin description …continued All digital inputs and bidirectional pins are 5 V tolerant. Symbol Pin DM_CE_1 102 INT1 103 DM_DATA_0 104 VSSD3 105 VDDD3 106 EF 107 DM_DATA_1 108 DATA 109 DM_DATA_2 110 WCLK 111 DM_DATA_3 112 SCLK 113 DM_DATA_4 ...
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... NXP Semiconductors Table 2. Pin description …continued All digital inputs and bidirectional pins are 5 V tolerant. Symbol Pin RA 142 FO 143 n.c. 144 [1] See Table 3 for pin type definition. Table 3. Type AI AO AIO AIB ID IDH IU IUH Functional description 6.1 Analog data acquisition The input signals from the OPU photodiodes contain information used in the servo loops and the high frequency data from which the audio samples are reconstructed ...
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... NXP Semiconductors Relative gain mismatch is minimized by using carefully scaled circuitry in the time-continuous parts of the signal path, and by time-sharing circuitry in the time-discrete parts. A simplified block diagram of the LF acquisition path is shown in AUX_L, AUX_R, GPIO1, GPIO3 D1, D2, GPIO0, GPIO2 anti-alias filter (only used on GP inputs) (1) if_auxin_sel = 0: D1 and D2 selected ...
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... NXP Semiconductors 6.1.2 HF acquisition The HF data (EFM) signal is obtained by summing the signals from the three or four central diodes of the OPU and filtering and converting the signals to a digital representation via a 6-bit HF ADC. path. RFControl2[5] register RFControl2[1] HF_MON Fig 4. The four diode signals D1, D2, D3 and D4 are summed in the first RF amplifier. The gain of the fi ...
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... NXP Semiconductors To help users set up the correct gain and DC offset for each particular mechanism, an eye pattern monitor facility is included. This consists of a high frequency buffer amplifier whose input can be selected to monitor various important nodes within the analog RF path. The monitor point is controlled by register RFControl1[6:4] field RFMONSEL. The output of the buffer drives HF_MON pin (pin 7). This register also controls the roll-off frequency of the noise fi ...
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... NXP Semiconductors that can decrease the quality of audio. The clocks related to audio DAC and LF ADC are generated directly from the analog signal, instead of being derived from high frequency PLLs. The clocking strategy for the digital core is shown in 6.3 General purpose analog inputs ...
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... NXP Semiconductors MUX D1 or AUX_L AUX_L 2 C spare reg A MUX D2 or AUX_R AUX_R 2 C lf_auxin_sel (1) 10-bit samples of AUX_L and AUX_R expanded to 16 bits by adding 6 LSBs router block used to route I Fig 6. Auxiliary analog inputs block diagram SAF784X_2 Product data sheet One chip CD audio device with integrated MP3/WMA decoder ...
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OSC_32K_IN 152 MHz subsys clock CLOCK GENERATOR ARM RAM ROM ARM / AHB 8.4672 MHz PDSIC clock 32 kHz clock RTC GPIO VPB slaves clock 2 8.4672 MHz I C clock bit clock Fig 7. Clocking top-level ...
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... NXP Semiconductors 6.5 Channel decoder 6.5.1 Features The channel decoder in the SAF784x is derived from the design used in the SAA7817HL DVD decoder IC. The design has been optimized for CD decode functionality (EFM and demodulation is removed) and has the following features: • One-channel interface to the on-chip 6-bit 67 MHz ADC • ...
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... NXP Semiconductors and CD-text decoder, available for readout through the sub-CPU interface. The main data stream is error-corrected by the ERCO, while the memory processor takes care of the CIRC de-interleaving and buffering of data in a FIFO. At the back end of the channel decoder, corrupted audio samples can be interpolated and held, while a burst of errors can trigger the mute block ...
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INTEGRATE diode ANALOG ADC AND signals DUMP 0 3000 00A0 PEAK DETECTORS 0 3000 0060 to 0 3000 00A0 AGC AOC 0 3000 01B0 to 0 3000 01BC CD-TEXT 0 3000 01A0 to 0 3000 01A8 Q-SUBCODE ...
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... NXP Semiconductors 6.5.3 Clock control (1) 66 MHz is an approximate value. Fig 9. The clock control block defines the clock frequencies for four clock domains. SAF784X_2 Product data sheet One chip CD audio device with integrated MP3/WMA decoder INTEGRATE AND DUMP hf_clk (66 MHz) sysclk ...
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... NXP Semiconductors • xclk: most internal clocks are derived from the crystal clock. This clock is the output of the clock multiplier in the analog part and has a fixed frequency of 67.7376 MHz = 8.4672 MHz (f inside the analog block. Crystal selection is done via AnalPLLControl bit SEL16. ...
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... NXP Semiconductors For the application, it should be noted that the interface supports 32-bit registers, while the decoder only contains 8-bit registers. Therefore, the decoder registers are treated as 32-bit registers of which the 24 MSBs are not used. The register address map occupied by the decoder goes from relative address 0x3000 0000 to address 0x3000 0374, and can be split into two parts: 0x3000 0000 - 0x3000 024C: the decoder’ ...
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... NXP Semiconductors The detected bits are then sent to the demodulator for sync extraction and EFM demodulation. For playing on damaged or out-of-specification discs, flywheels are in place to make the sync extraction more robust. 6.5.5.1 Signal conditioning This device has a number of blocks which process the incoming 6-bit HF signal. ...
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... NXP Semiconductors The high-pass filter works on the system clock. Its bandwidth is also proportional to the sysclk. A formula for approximating the cut-off frequency ( HPF Peak Detectors: • peak detector with decay filter: works on an immediate attack/slow-decay basis, and is used for measuring peaks, amplitude and offset, read by software which sends peak information to the defect detector. • ...
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... NXP Semiconductors The bandwidths and corresponding time-constant (t) of the decay filter are shown in Table 4, when the system clock frequency f Table Peak detector based on window: shown in Fig 13. Peak detection block with window The minimum and maximum peaks of the incoming signal are measured during a programmable window period ...
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... NXP Semiconductors G1 HPF ANALOG 6 MSBs INTEGRATOR 4 MSBs INTEGRATOR Fig 14. AGC and AOC loops The maximum and minimum peaks on the envelope of the RF signal after the ADC are first measured via a noise filter and the window peak detector (see Detectors” on page offset as (maxpeak + minpeak ...
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... NXP Semiconductors correction range of compensation (offset comp) value can be programmed via register OffsetComp, and will be regulated in hardware as soon as the AOC is turned on. The AOC will regulate the offset comp value such that the measured offset stays within a window programmed by register OffsetBound. The offset comp value decreases if the offset is above this window, and increases if the offset is below the window ...
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... NXP Semiconductors The detection of a defect is based on amplitude. The amplitude is measured via a set of peak detectors with decay, as described in decay bandwidth and noise filter bandwidth are programmed by register DefectDetPeakBW. Two thresholds can be programmed. A low threshold will trigger a ‘defect-detected’ signal as soon as amplitude goes below this threshold. A high threshold will clear this ‘ ...
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... NXP Semiconductors 6.5.5.2 Bit detector signal conditioning Fig 15. Bit detector block diagram The bit detector block contains the slice-level circuitry, a noise filter to limit HF EFM signal noise contribution, an equalizer, a zero-transition detector, a run-length push-back circuit, a digital PLL and jitter measurement logic. All processing is performed on the bit clock, and bandwidths are proportional to the channel bit rate. To achieve this, RF data is resampled from the system clock domain to the bitclk domain by making use of a sample-rate convertor. Blocks can be confi ...
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... NXP Semiconductors Fig 16. Equalizer block diagram The first and last tap can be programmed via register PLLEqualiser. Usable EFM bit clock range: following constraints in relation to the system clock frequency f clock frequency must always be: • less than f • greater than f Therefore the range is reliable bit detection is only possible within this range ...
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... NXP Semiconductors Fig 17. PLL bode diagram f : Integrator cross-over controlled via PLL bandwidth controlled via LPF bandwidth controlled via K 2 The three frequencies are programmable using register PLLBandWidth. The higher bandwidths for use after a defect, are programmed in register PLLBandWidthHigh; see Section “Defect detector” on page When the PLL is in lock, the recovered PLL clock frequency equals the channel bit clock frequency ...
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... NXP Semiconductors • optional manual selection of the PLL state (in-lock, inner-lock, outer-lock, outer-lock with only RL3 regulation). • optional pre-set of the PLL frequency to a certain value Overriding the PLL state: • In-lock • Inner lock • Outer lock • Outer lock with only RL3 regulation • ...
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... NXP Semiconductors 6.5.5.5 Available signals for monitoring The operation of the bit detector can be monitored by the microcontroller via an external pin. Five signals are available for measurement: PLL frequency signal: The microcontroller monitors this signal by reading register PLLIntegrator. Asymmetry signal: This signal is in 2’s complement form and can be read from register SlicerAssym ...
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... NXP Semiconductors • Analog preamplifier • ADC • Limited bandwidths in this device • Limited PLL performance • Influenced by internal noise filter, asymmetry compensation and equalizer The jitter measurement is absolute reference, because it relates directly to the EFM bit error rate if the disc noise is gaussian. ...
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... NXP Semiconductors Table 8. Bit [1] The start bit is always preceded by 17 pause bits. The intermediate start bits at bit locations 12, 24 and 36 guarantee that no other '1' value is preceded by 17 ‘0’ bits. This allows a simple start bit detection circuit. [2] The jitter word is sampled twice in every frame. ...
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... NXP Semiconductors To prevent such false demodulator re-syncs, two features are built in, which are both programmable via register DemodControl: • RobustCntResync: This feature should always be turned on: when it is on, the demodulator will look for three consecutive syncs instead of two, with correct in-between distance before re-syncing. This should greatly improve the robustness against false syncs. • ...
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... NXP Semiconductors Table 9. Address/Byte After finishing a subcode read, the microcontroller must release the interface to allow the decoder to capture new subcode information. This is done by issuing a read to register SubcodeQReadend. The availability of a new subcode frame will also trigger an interrupt if InterruptEnable2 bit SUBCODEREADYENABLE is set. ...
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... NXP Semiconductors 6.5.7 Main data decoding 6.5.7.1 Data processing The CD main data is de-interleaved and error-corrected according to the CD Red Book (IEC 60908) CIRC decoding standards, and uses an internal SRAM as buffer and FIFO. The C1 correction will correct up to two errors per EFM frame, and will flag all uncorrectable frames as an erasure. The C2 error correction will correct up to two errors or four erasures, and will also fl ...
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... NXP Semiconductors • Master (Flow Control) mode: selected when using a gated bit clock (bclk) at the I interface, see available in the FIFO output via the I imminent, the decoder gates the output interface by disabling bclk. • Slave (audio) mode: the bclk is continuously clocked in this mode. The application is ...
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... NXP Semiconductors The serial format consists of a pause bit followed by a start bit, followed by data bits. The format of the data is explained in Bit length: seven sysclk periods. Frame length: 11 bits. Table 10. Bit [1] The CFLG repetition rate is not fixed and depends on disc speed and output interface speed. There is always at least one pause bit ...
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... NXP Semiconductors Decoded and error-corrected CD data streams into the back end from the memory processor to the output interfaces; some audio filtering can be done in-between, when playing CD-DA for example. 6.5.9.1 Audio processing The following audio features are present in the back end: • ...
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... NXP Semiconductors 6.5.9.3 Soft mute and error detection The audio data going to the I block. This block can ramp the audio volume down from dB, making use of 64 stages of about 1.5 dB each. The current stage can be monitored and changed by software read or write register MuteVolume. This allows the implementation of a software mute scheme ...
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... NXP Semiconductors Fig 22. De-emphasis characteristics The de-emphasis filter is controlled via FilterConfig bit DEEMPHCONTROL. The filter can be enabled or disabled under software control, or automatically by hardware. In the latter case, the filter is turned on when a ‘pre-emphasis’ bit is detected in the control byte of the Q-channel subcode, and turned off when this bit is missing. ...
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... NXP Semiconductors Another result of the upsampling is that every sample will have 18-bit precision after the upsample filter instead of 16-bit. To make use of this extra bit precision, the user should 2 select I output. 6.5.9.8 Data output interfaces There are three interfaces via which data can be output from the channel decoder block. ...
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... NXP Semiconductors bclk and I output (generated internally in the clock control block). Selection can be done via WclkSel and BclkSel in register I2SConfig. 2 The I S output rate is determined by the speed of the I via register BitClockConfig. One can configure the speed. For a gated bit clock, when BitClockConfig bit BCLKGEN is HIGH, the speed must be confi ...
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... NXP Semiconductors wclk V4 V4_sync Fig 25. Subcode output (upsampling enabled) When slave mode is used (no I output port as a true single-line interface. In this case the receiver needs to sample the data on the line at a frequency half I synchronize the bit and byte detection in the stream in absence • ...
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... NXP Semiconductors The motor servo consists filter and a PWM or PDM modulator. When put in a closed loop, the motor controller can control both speed/frequency and position error (FIFO fill). It can be operated controller, by switching on and off the appropriate switches (sw1, sw2). The frequency and position error integrator gain, K programmable. Frequency and fi ...
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... NXP Semiconductors • Kf_mult operates by sampling the input. For example, for Kf_mult = 1, every sample of the input is passed through to the integrator circuit, for a Kf_mult of 0.5, every second sample is passed through, for a Kf_mult of 0.25, every fourth sample is passed through, and so on. • For a DC input signal, K ...
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... NXP Semiconductors 6.5.10.7 Tacho Fig 27. Tacho block diagram The tacho circuit accepts the tacho input on the tacho inputs T1, T2 and T3, coming from the hall sensors on the spindle motor. The Tacho block measures the frequency of the input pulses, and filters the measurements using a second-order low-pass filter to remove noise on the tacho signal ...
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... NXP Semiconductors Tacho trip frequency: reaching a specific speed during spin-up or spin-down. This is done by programming the desired frequency trip point in register TACHO2. When the tacho frequency goes above or below this trip point, an interrupt gets generated (bit 3 of register InterruptStatus2). Bit 1 (TACHOINTERRUPTSELECT) of register TACHO3 can be set to enable an interrupt to be generated when the frequency goes above or below the trip point ...
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... NXP Semiconductors command byte and its full compliment of parameter bytes). At this point, the PDSIC acts upon the command and the appropriate function is carried out based upon the values in the stack space. There are two special case servo commands: Write_parameter (opcode = 0xA2) and Write_decoder_reg (opcode = 0xD1) ...
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... NXP Semiconductors srv_fc0 srv_fc1 IRQ inreq_clr Fig 28. Function of servo IRQ signal with respect to srv_fc0, srv_fc1 and inreq_clr The SAF784x contains additional circuits to implement a servo feature called Flexi servo. The purpose of the flexible servo system is, in conjunction with the existing analog and digital LF path, to provide maximum fl ...
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... NXP Semiconductors 6.6.3 Signal conditioning The digital codes retrieved from the ADC and PDM generator are applied to logic circuitry to obtain the various control signals. The signals from the central aperture diodes are processed to obtain a normalized focus error signal where the detector setup is assumed shown in ...
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... NXP Semiconductors Fig 29. Detector arrangement 6.6.4 Focus servo system 6.6.4.1 Focus start-up The start-up behavior of the focus controller is influenced by five initially loaded coefficients. The automatically-generated triangular voltage can be influenced by three parameters: height (ramp_height), DC offset (ramp_offset) of the triangle, and its steepness (ramp_incr) ...
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... NXP Semiconductors Fig 30. Bode diagram of focus PID system A simplified block diagram of the focus PID system is given in focus error, FE defect or shock Fig 31. Block diagram of focus PID system The actuator position can be held by using a zero error signal. This action is taken if a defect or shock is encountered. The PID is followed by a low-pass filter to reduce audible noise in the control loop ...
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... NXP Semiconductors 6.6.4.3 Dropout detection This detector can be influenced by one parameter (CA_drop). Focus will be lost and the integrator of the PID will hold if the CA signal drops below this programmable absolute CA level. When focus is lost it is assumed, initially caused by a black dot. ...
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... NXP Semiconductors Table 13. Parameter Fig 33. Bode diagram of radial PID system 6.6.5.2 Level initialization During startup, an automatic adjustment procedure is activated to set the values of the radial error gain (re_gain), offset (re_offset) and satellite sum gain (sum_gain) for TPI level generation. The initialization procedure runs in a radial open loop situation and is 300 ms ...
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... NXP Semiconductors 6.6.5.4 Focus loss detection and fast restart Whenever focus is lost for longer than approximately assumed that the focus point is lost. A fast restart procedure is initiated which is capable of restarting the focus loop within 200 ms to 300 ms depending on the programmed coefficients of the microcontroller ...
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... NXP Semiconductors voltage on the radial actuator and provide the sledge with step pulses to reduce power consumption. Filter coefficients of the continuous sledge control can be preset by the user. 6.6.6.4 Access The access procedure is divided into two different modes depending on the requested jump size; see Table 14 ...
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... NXP Semiconductors These signals can have uncertainties caused by: • Disc defects such as scratches and fingerprints • The HF information on the disc; which is considered as noise by the detector signals In order to determine the spot position with sufficient accuracy, extra conditions are necessary to generate a Track Loss (TL) signal and an off-track counter value. These extra conditions infl ...
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... NXP Semiconductors • Radial play: started when radial servo is in On-track mode and a first subcode frame is found; detects when maximum time between two subcode frames exceeds the time set by the playwatchtime parameter; then sets radial error interrupt, switches radial and sledge servos off, and puts disc motor in jump mode • ...
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... NXP Semiconductors • Sigma-delta noise shaper: this block regenerates a PDM data stream from a given multi-bit value, which is provided at its inputs. 6.7.1 Modes of operation The flexible servo can be used in six main modes, they are described in the following sections. 6.7.1.1 Hardware servo-only This mode uses the hardware servo (PDSIC) only without any additional processing taking place on either the diode input signals or the servo output signals. 6.7.1.2 Hardware servo with fi ...
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... NXP Semiconductors 6.8 Block decoder The general features of the SAF784x block decoder are: • 32-bit microprocessor interface • Channel decoder compatible C2I interface • Segmentation manager compatible MiMeD2 interface The main CD decode features of the SAF784x block decoder are: • 16-bit data channel • ...
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... NXP Semiconductors AHB bus ARM AHB REGISTER INTERFACE CD-ROM CD-ROM SYNC DE-SCRAMBLER DETECTOR CD main data C2I CHANNEL CD subcode data DECODER INTERFACE Fig 35. Block decoder data path 6.8.1 Supported modes of operation The block decoder supports CD-DA and CD-ROM decode transfers. CD main data and subcode data are received from CD-Slim over the C2I interface. The main data is processed by the decode main data path functions before being passed to the memory controller ...
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... NXP Semiconductors The alignment between the main channel and the subcode channel must be the same each time a sector is read. 6.8.3 Block decoder to segmentation manager interface The MiMeD2 interface is the data interface between the block decoder and the SAF784x segment manager asynchronous interface; the block decoder and SAF784x segment manager operate in independent clock domains ...
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... NXP Semiconductors Once the interrupt has been triggered, it will remain asserted until cleared by the Inreq_Clr signal. However, after being cleared then free to fire again on the next transition. Note that the register bit INREQ_CLR retains the latest value written by the ARM processor so a typical sequence will be to write logic 0 followed some time later by logic 1 in order to return to the non-reset state ...
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... NXP Semiconductors 6.10 Laser interface The laser diode pre-amp function is built in to the SAF784x and is illustrated in The current 120 mA, can be regulated in four steps ranging from full power. The voltage derived from the monitor diode is maintained at a steady state by the laser drive circuitry, regulating the current through the laser diode. ...
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... NXP Semiconductors Table 15. Process technology 0.18 m [1] The frequency of operation depends on the performance required for the SAA7834 application and the software complexity. MP3/WMA decoding requires most high-speed peripherals to operate at this frequency. The MP3/WMA decoding library is implemented in software. The ARM7TDMI-S processor has two instruction sets: 1 ...
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... NXP Semiconductors • AMBA AHB-compliant • Asynchronous burst mode read access from burst mode ROM and Flash devices • Asynchronous page mode read access in non-clocked memories • 8-bit and 16-bit wide data paths • Independent configuration of two memory banks, with maximum access each • ...
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... NXP Semiconductors 7.2.3 Read access to external memories The sections below describe the step-by-step process required for setting up the static memory interface unit registers prior to accessing the external memory. 7.2.3.1 Programming the external memory data widths The bank configuration register SMBCRx (x = bank number 1), is used to describe the bus width ...
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ARM external processor memory read/write control data read by the arm processor address at the memory output enable /chip select to the memory data read from the ...
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... NXP Semiconductors 7.2.3.4 Burst reads from external memory The static memory control unit can support a maximum of four consecutive reads from external reads. This feature supports burst mode ROM devices. This feature increases the bandwidth for sequential reads compared to non-sequential reads. The burst access requires the user to specify the access times in SMBWST2x; for single reads, the access times are specifi ...
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... NXP Semiconductors • Maximum ARM operating frequency for the SAF784x: for applications supporting WMA decoding, the ARM operating frequency is fixed at 76 MHz • External memory access times: critical for determining the allowable delay that programmed via software, or the delay through the hardware The equation for read latency delay for sequential reads ...
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... NXP Semiconductors 7.5 Embedded KFlash interface The KFlash controller is an interface between the embedded Flash memory device and AHB bus. The AHB embedded Flash controller connects embedded Flash memory devices to the AHB bus. The embedded Flash controller supports full AHB bus protocol and will never generate a retry or split response. The data path between the memory and the controller is fi ...
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... NXP Semiconductors • 8.4672 MHz I • FIFO depth • FIFO depth • Maximum I • Compatible with 7-bit and 10-bit addressing 7.8 General purpose I/Os The GPIOs are linked to the VPB bus. This interface provides individual control over each bidirectional pin. Each pin can be configured input, output or bidirectional: • ...
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... NXP Semiconductors 7.11 Timers • Conforms to the VLSI Peripheral Bus (VPB) interface specification • Clock prescaler for external high-frequency sources • The VPB timer operates in two fully independent clock domains: – vpb_clk for accessing control and status registers (76 MHz maximum) – ...
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... NXP Semiconductors For memory-to-memory transfers, the length of the operation is specified. When half of this length is reached, or when the end of the transfer has been reached, the CPU can be interrupted or the CPU can poll for notification of this event. The SDMA controller has a maximum of six channels, each channel can be configured with its own source, destination, length and control information ...
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... NXP Semiconductors Fig 39. VSRC block diagram 7.15.3 EBU interface The channel decoder contains a digital 1-wire EBU or S/PDIF output interface. It formats data according to specification IEC 958. The EBU rate can be selected CD-speed or 2 CD-speed. For proper operation of the EBU interface, the I ...
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... NXP Semiconductors The requirement for reset is the availability of the clocks during synchronous reset de-assertion. 7.16.3 Assertion of reset The polarity of reset assertion is active LOW. During reset assertion the internal logic is initialized into the correct state. Due to the nature of complex logic, the initialization time may not be instantaneous ...
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... NXP Semiconductors 9. Recommended operating conditions Table 17. Symbol V DDD(C) V DDD V DDA T amb 10. Characteristics Table 18. Characteristics 3 3 DDD DDA DDD(C) Symbol Parameter Supply ( +85 C) amb V core digital supply voltage DDD(C) V digital supply voltage DDD V analog supply voltage DDA I core digital supply current DDD(C) ...
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... NXP Semiconductors Table 18. Characteristics …continued 3 3 DDD DDA DDD(C) Symbol Parameter V peak-to-peak differential input I(dif)(p-p) voltage V common-mode input voltage I(cm) B bandwidth t phase delay time variation d( ) S/N signal-to-noise ratio V peak-to-peak single-ended ADC i(ADC)se(p-p) input voltage THD total harmonic distortion PSRR power supply rejection ratio ...
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... NXP Semiconductors Table 18. Characteristics …continued 3 3 DDD DDA DDD(C) Symbol Parameter Pin: OSCOUT f oscillator frequency osc g transconductance m C feedback capacitance fbck C output capacitance o R internal bias resistance bias(int) Real time clock oscillator Pin: OSC_32K_IN (external clock) V LOW-level input voltage IL V HIGH-level input voltage ...
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... NXP Semiconductors Table 18. Characteristics …continued 3 3 DDD DDA DDD(C) Symbol Parameter I HIGH-level output current OH I LOW-level output current OL I HIGH-level short-circuit output OSH current I LOW-level short-circuit output OSL current I pull-down current pd I pull-up current pu AC specifications; input t rise time r t fall time f AC specifi ...
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... NXP Semiconductors 11. Test information 11.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 - Stress test qualification for integrated circuits , and is suitable for use in automotive applications. SAF784X_2 Product data sheet One chip CD audio device with integrated MP3/WMA decoder Rev. 02 — ...
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... NXP Semiconductors 12. Package outline LQFP144: plastic low profile quad flat package; 144 leads; body 1 108 109 pin 1 index 144 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 0.27 mm 1.6 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 42. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 14. Abbreviations Table 21. Acronym ACU ADC AGC AHB ALU AMBA AOC ARM BLER Cn CA CAV ...
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... NXP Semiconductors Table 21. Acronym CIRC CLV CPU CRC DAC DEM DAC DC DMA EFM ERCO FIFO GPAI GPIO HDLi HF HPF HSI ICE IIR IRQ LF LPF LSB MiMeD2 MP3 MSB MSF NF OPU PDM PDSIC PI PID PLL PSRAM PWM RAM RE RISC RL SAF784X_2 Product data sheet ...
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... NXP Semiconductors Table 21. Acronym ROM RTC SACD SMIU S/PDIF SRAM SRC TPI UART VLSI VPB VSRC WDT WMA 15. Glossary ARM7TDMI-S — Specific version of ARM microprocessor used in the SAF784x (ARM7 family) Dark currents — Currents caused by unwanted light leakage into the OPU causing offsets, otherwise known as dark current offsets Flexi servo — ...
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... NXP Semiconductors 16. Revision history Table 22. Revision history Document ID Release date SAF784X_2 20080509 • Modifications: Table 18 • Replaced instances of <tbd> with text or values in SAF784X_1 20071214 SAF784X_2 Product data sheet One chip CD audio device with integrated MP3/WMA decoder Data sheet status Product data sheet “ ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Formats Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 9 6.1 Analog data acquisition 6.1.1 LF acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.1.2 HF acquisition . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.2 Analog clock generation . . . . . . . . . . . . . . . . . 12 6.3 General purpose analog inputs . . . . . . . . . . . 13 6 ...
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... NXP Semiconductors 6.6.10.1 Automatic error handling 6.6.10.2 Automatic sequencers and timer interrupts . . 60 6.6.11 Driver interface . . . . . . . . . . . . . . . . . . . . . . . . 60 6.7 Flexi servo options . . . . . . . . . . . . . . . . . . . . . 60 6.7.1 Modes of operation . . . . . . . . . . . . . . . . . . . . . 61 6.7.1.1 Hardware servo-only 6.7.1.2 Hardware servo with fine offset compensation . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.7.1.3 Fully flexible servo . . . . . . . . . . . . . . . . . . . . . 61 6.7.1.4 Pre-processing with hardware servo . . . . . . . 61 6 ...