SAF7849HL/M295,557 NXP Semiconductors, SAF7849HL/M295,557 Datasheet - Page 28

• Manufacturer Part Number: SAF7849HL/M295,557
• Description: IC AUD DECODER 144LQFP
• Manufacturer: NXP Semiconductors
• Type: Audio Decoderr

Specifications of SAF7849HL/M295,557

• Applications: Audio CD
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 1.8V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935287932557

NXP Semiconductors
SAF784X_2
Product data sheet
6.5.5.2 Bit detector
The bit detector block contains the slice-level circuitry, a noise filter to limit HF EFM signal
noise contribution, an equalizer, a zero-transition detector, a run-length push-back circuit,
a digital PLL and jitter measurement logic.
All processing is performed on the bit clock, and bandwidths are proportional to the
channel bit rate. To achieve this, RF data is resampled from the system clock domain to
the bitclk domain by making use of a sample-rate convertor. Blocks can be configured
under microcontroller control and are described in detail in the next paragraphs.
Noise filter:
limits the bandwidth of the incoming signal to
Passband: 0
Stop-band: (0.28
Rejection: 28 dB
Slice-level determination:
incoming signal asymmetry component. Bandwidth of the slice-level determination circuit
is programmable via register SlicerBandwidth. Also the higher bandwidths for use after a
defect (see
bandwidth is proportional to the channel bit clock frequency. The slice level, or asymmetry,
can be read back via register SlicerAssym.
Equalizer:
frequency content of the incoming signal.
The equalizer includes an integral five-tap presentable, asymmetrical equalizer. The
equalizer block diagram is given in
Fig 15. Bit detector block diagram
conditioning
signal
from
In the bit detection circuit, a programmable equalizer is used to boost the high
Section “Defect detector” on page
The digital noise filter runs on the channel bit clock frequency f
f
clk(bit)ch
f
clk(bit)ch
to 0.22
One chip CD audio device with integrated MP3/WMA decoder
SRC
Rev. 02 — 9 May 2008
) to (f
The slice-level determination circuit compensates for the
DETERMINE
FILTER
clk(bit)ch
NOISE
LEVEL
SLICE
f
clk(bit)ch
Figure
(Hz)
0.28
EQUALIZER
16.
DIGITAL
clocked on
PLL clock
DIGITAL
1
PLL
26) are programmed in this register. The
4
f
of the channel bit clock frequency.
clk(bit)ch
MEASUREMENT
) (Hz)
PLL frequency
TRANSITION
JITTER
PUSHBACK
jitter value
slice level
RMS
DETECT
ZERO
RL2
multiplex
SAF784x
© NXP B.V. 2008. All rights reserved.
Meas1
to demodulator
clk(bit)ch
001aag319
. It
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