SAF7849HL/M295,557 NXP Semiconductors, SAF7849HL/M295,557 Datasheet - Page 50

• Manufacturer Part Number: SAF7849HL/M295,557
• Description: IC AUD DECODER 144LQFP
• Manufacturer: NXP Semiconductors
• Type: Audio Decoderr

Specifications of SAF7849HL/M295,557

• Applications: Audio CD
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 1.8V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935287932557

NXP Semiconductors
SAF784X_2
Product data sheet
command byte and its full compliment of parameter bytes). At this point, the PDSIC acts
upon the command and the appropriate function is carried out based upon the values in
the stack space.
There are two special case servo commands: Write_parameter (opcode = 0xA2) and
Write_decoder_reg (opcode = 0xD1).
Write_parameter allows the microcontroller to write directly to any memory location. It
carries two parameter bytes: the memory address and the data that is to be written. When
this command is executed, the command byte is loaded into oldcom and the first
parameter byte (RAM_address) is loaded in the stack. The second parameter byte (data)
is loaded directly to the location specified by the RAM_address.
Write_decoder_reg allows decoder registers to be written to when the I
being used. This command carries only one parameter byte, which is the decoder
register/data pair (two nibbles). When this command is received by the PDSIC, the
register/data pair is loaded into memory location 0x4D.
The servo read commands operate slightly differently because they carry no parameter
bytes and the lower nibble of the command byte is always 0 to indicate this. When the
PDSIC receives a read command, it will make certain information available (mostly from
memory, although some status information is retrieved from the decoder) on the serial
interface for collection by the microcontroller.
If a sequence of values is being read from the servo RAM (e.g. a series of values related
to a PID loop), it is important to ensure that the values are consistent with each other by
ensuring that the servo has not updated some of the values during the period that they are
being read. To prevent this occurring, an interrupt signal is available from the servo to the
ARM which asserts an IRQ when it is safe to read related values. The interrupt generator
monitors these signals and raises an IRQ whenever the correct state is achieved. The
interrupt is cleared by applying a pulse to the Inreq_Clr register bit. If the interrupt is not
cleared, it will automatically be reset when the valid reading state is no longer true.
Figure 28
interrupt that does not get cleared by the ARM. Int #2 and Int #3 are shown being cleared
by pulses being written to the Inreq_Clr register. The time between interrupts is
approximately 15 s and the total interrupt cycle time is about 60 s.
shows the operation of the IRQ signal. Int #1 shows the full duration of an
One chip CD audio device with integrated MP3/WMA decoder
Rev. 02 — 9 May 2008
SAF784x
2
© NXP B.V. 2008. All rights reserved.
C-bus interface is
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