SAF7849HL/M295,557 NXP Semiconductors, SAF7849HL/M295,557 Datasheet - Page 20

• Manufacturer Part Number: SAF7849HL/M295,557
• Description: IC AUD DECODER 144LQFP
• Manufacturer: NXP Semiconductors
• Type: Audio Decoderr

Specifications of SAF7849HL/M295,557

• Applications: Audio CD
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 1.8V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935287932557

NXP Semiconductors
SAF784X_2
Product data sheet
6.5.4.1 Programming interface
6.5.4 Decoder-ARM microprocessor interface
The decoder core is internally connected to the ARM core via the AHB interface for
register access to the decoder internal configuration registers.
Decoder registers are programmed through the AHB interface. The programming
interface is not fully described in this document.
•
•
•
•
xclk: most internal clocks are derived from the crystal clock. This clock is the output of
the clock multiplier in the analog part and has a fixed frequency of 67.7376 MHz
= 8.4672 MHz (f
inside the analog block. Crystal selection is done via AnalPLLControl bit SEL16.
sysclk domain: the system clock, or its derivatives, runs the main part of the internal
channel decoder. The sysclk is derived from xclk divided by 2 (50 % duty cycle) and
can be further divided down via register SysclockConfig bit SYSDIV. This register also
allows the majority of clocks to be powered down (for Sleep mode). The choice of the
sysclk frequency f
f
and the system clock frequency f
two limiting factors:
– The HF-PLL operating range is between 0.25
– The decoder and error corrector throughput rate is limited to 1.7
This brings the constraint to 0.25 < f
bitclk domain: runs the I
of the I
44100 Hz
DAC. In master mode with gated bitclk, the bitclk must be programmed to be at a
higher rate than the outgoing bit rate required for the disc speed, to avoid FIFO
overflow in the decoder. For example, at N = 1, the incoming RF bit rate =
4.3218 MHz, which corresponds to an output bit rate of 1.4112 MHz. This means that
the bitclk frequency is above 1.4112 MHz and is high enough when I
while I
selected via register BitClockConfig. Also, bitclk gating can be enabled via the same
register.
ebuclk domain: runs the EBU back end. The EBU (or S/PDIF) interface is only
enabled during audio slave mode. The ebuclk needs to be exactly
44100 Hz
register EBUClockConfig.
The following clocks are also controlled by the clock control block:
– The hf_clk is fixed at 67.7376 MHz, and is used to clock-in the samples from the
– The bclk_in is the incoming I
– The cl1clk can be used to monitor the Cflg and Meas1 debug lines. The frequency
– The cl16clk can be used to clock an external audio DAC or audio filter IC. The
bit
ADC, which is clocked by the xclk with the same clock frequency
receive bclk rather than transmitting it (programmed via register I2SConfig)
can be programmed via register CLClockConfig
frequency can be programmed via register CLClockConfig
of the RF bit stream. The relationship between this incoming bit stream frequency
2
2
S-32 requires the bitclk to be at least 2.8224 MHz. The bitclk division is
S interface. In audio slave mode this clock must be programmed to be exactly
2
64 = 2.8224 MHz for 1 operation. The ebuclk division is selected via
xtal
16/24/32 (depending on I
clk(sys)
)
One chip CD audio device with integrated MP3/WMA decoder
Rev. 02 — 9 May 2008
8. If a 16 MHz crystal is used, the crystal clock is divided by 2
2
in an application is determined by the expected input bit rate
S back-end logic. The bit clock (bitclk) is also output as part
2
S bit clock, which is used when I
clk(sys)
bit
/ f
is expressed by the ratio f
clk(sys)
2
S mode), to get a 1 data rate to the audio
< 1.7.
(f
bit
/ f
clk(sys)
) and 2
bit
2
S is programmed to
SAF784x
/ f
© NXP B.V. 2008. All rights reserved.
clk(sys)
2
(f
S-16 is chosen,
bit
(f
bit
/ f
. There are
clk(sys)
/ f
clk(sys)
20 of 93
)
)