SAF7849HL/M295,557 NXP Semiconductors, SAF7849HL/M295,557 Datasheet - Page 75

• Manufacturer Part Number: SAF7849HL/M295,557
• Description: IC AUD DECODER 144LQFP
• Manufacturer: NXP Semiconductors
• Type: Audio Decoderr

Specifications of SAF7849HL/M295,557

• Applications: Audio CD
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 1.8V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935287932557

NXP Semiconductors
SAF784X_2
Product data sheet
7.11 Timers
7.12 Watchdog timer
7.13 Real-time clock
7.14 DMA controller
The Single operation DMA interface (SDMA), is a small AHB bus master specifically
designed for bulk memory transfers over the ARM AHB bus.
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Conforms to the VLSI Peripheral Bus (VPB) interface specification
Clock prescaler for external high-frequency sources
The VPB timer operates in two fully independent clock domains:
– vpb_clk for accessing control and status registers (76 MHz maximum)
– timer_clk for the timer/counter function (50 MHz maximum)
The VPB timer can support up to four match registers having:
– Continuous operation with optional interrupt generation on match
– Stop on match, with or without, interrupt generation
– Reset on match, with or without, interrupt generation
Optional external match notification pins with the following features:
– Set LOW on match
– Set HIGH on match
– Toggle on match
– No action on match
Up to four capture registers and capture trigger pins with optional interrupt generation
on a capture event
Interrupt generation on match event and capture event
Configurable watchdog feature including:
– Watchdog timer restart trigger protection by key
– Watchdog timer reload value protection by key access sequence
– Watchdog timer reset disable (for debug) protection by key
Interrupt generation watchdog time-out event
Zero wait-state to access all registers from the VPB interface
Provide coherent fraction and seconds time
Requirement for external 32 kHz crystal
Alarm and tick interrupts will be generated even when the VPB clock is switched off
VPB RTC interrupt
Real-time clock and VPB clock may be asynchronous (the VPB clock frequency could
be higher or lower than the RTC clock frequency)
Maximum VPB slave frequency: 50 MHz
One chip CD audio device with integrated MP3/WMA decoder
Rev. 02 — 9 May 2008
SAF784x
© NXP B.V. 2008. All rights reserved.
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