SAF7849HL/M295,557 NXP Semiconductors, SAF7849HL/M295,557 Datasheet - Page 34

• Manufacturer Part Number: SAF7849HL/M295,557
• Description: IC AUD DECODER 144LQFP
• Manufacturer: NXP Semiconductors
• Type: Audio Decoderr

Specifications of SAF7849HL/M295,557

• Applications: Audio CD
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 1.8V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935287932557

NXP Semiconductors
SAF784X_2
Product data sheet
6.5.5.10 EFM demodulation
6.5.5.11 Sync detection and synchronization
6.5.5.12 Sync protection
6.5.5.9 Demodulator
Table 8.
[1]
[2]
The demodulator block performs the following functions:
Each EFM word of 14 channel bits (which are separated from each other by three merging
bits) is demodulated into one data byte making use of the standard logic array
demodulation as described in the CD Red Book (IEC 60908) .
The EFM sync pattern is a unique pattern which is not used anywhere else in the EFM
data stream. It consists of 24 bits: RL11 + RL11 + RL2. An internal sync pulse is
generated when two successive RL11s are detected. A sub-sync pulse is produced when
the beginning of a new subcode frame is seen. This is done by analyzing the subcode
information: when two successive subcodes are subcode sync-code S0 and S1, sub-sync
will be activated.
The sub-sync pulse is protected by an interpolation counter, this counter uses the fact that
a subcode frame is always 98 subcode symbols long.
The sync signal itself is also interpolated. If after 33 data bytes (one EFM frame), no new
sync is detected, it is assumed that the bit detector has failed to correctly produce it, and
the sync signal is given anyway, this is generally called an ‘interpolated sync.’
Furthermore, if a new sync is detected in the data shortly after a previous sync signal,
interpolated or real, no new sync signal will be produced, because this means the frame
has ‘slipped’. After enough data byte periods, the sync signals are allowed to pass again.
Although the possibility is small, ‘false syncs’ can be detected, such as corrupted EFM
bits that accidentally form the combination RL11 + RL11. If two, or three, of such false
re-syncs are detected at the correct distance from each other, this would cause a false
sync of the demodulator. Such a re-sync could lead to a large number of samples being
corrupted at the output of the CIRC decoder. The chance of false sync detection is
greatest during defects (black and white dots).
jitter
Bit
36
37 to 46
47 to 63
•
•
•
The start bit is always preceded by 17 pause bits. The intermediate start bits at bit locations 12, 24 and 36
guarantee that no other '1' value is preceded by 17 ‘0’ bits. This allows a simple start bit detection circuit.
The jitter word is sampled twice in every frame.
The percentage jitter is calculated using
EFM demodulation using a logic array
Sync detection and synchronization
Sync protection
=
---------------------------------------------- -
jitter 9:0
Data format on measurement pin CL1
4096
–
12.81
One chip CD audio device with integrated MP3/WMA decoder
Rev. 02 — 9 May 2008
100 %
Value
'1'
jitter(9) to jitter(0)
'0'
Equation
5:
…continued
Description
intermediate start bit
second sample of jitter word
pause
SAF784x
© NXP B.V. 2008. All rights reserved.
34 of 93
[2]
(5)