SAF7849HL/M295,557 NXP Semiconductors, SAF7849HL/M295,557 Datasheet - Page 21

• Manufacturer Part Number: SAF7849HL/M295,557
• Description: IC AUD DECODER 144LQFP
• Manufacturer: NXP Semiconductors
• Type: Audio Decoderr

Specifications of SAF7849HL/M295,557

• Applications: Audio CD
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 1.8V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935287932557

NXP Semiconductors
SAF784X_2
Product data sheet
6.5.4.2 Interrupt strategy
6.5.5 EFM bit detection and demodulation
For the application, it should be noted that the interface supports 32-bit registers, while the
decoder only contains 8-bit registers. Therefore, the decoder registers are treated as
32-bit registers of which the 24 MSBs are not used.
The register address map occupied by the decoder goes from relative address
0x3000 0000 to address 0x3000 0374, and can be split into two parts:
The channel decoder contains two interrupt status registers: InterruptStatus1 contains all
interrupts that operate as set/reset latches (set by hardware, reset by reading from the
register). InterruptStatus2 contains all interrupts that operate as feed-throughs (set by
hardware, reset by hardware or by accessing other registers).
Each interrupt bit can be enabled or disabled separately by writing to its corresponding
enable bit in the InterruptEnable1 and InterruptEnable2 registers. If one or several
interrupt bits are set and at least one is enabled, the interrupt line of the decoder to the
microcontroller will go active (LOW). If an interrupt bit is disabled (enable bit turned off), it
is prevented from activating the interrupt line to the microcontroller. However, this mode
allows the interrupt to be processed if the status register is polled instead of interrupt
handling by the microcontroller.
A block diagram of the bit recovery is shown in
The HF signal comprises the four diode inputs inside the analog block. It is pre-processed
(LPF, HPF, offset removal and gain adjustment) and then sampled by a 6-bit ADC.
On the sampled HF, bit recovery is done by means of a full digital PLL and slicer.
Before the sampled signal enters the PLL section, it is pre-processed by a signal
conditioning block. This consists of an integrate-and-dump block, a high-pass filter and
logic available for gain control and offset control on the RF signal in the analog section.
For good playability on defects, a defect detector puts the PLL, the slicer, the AGC, the
offset cancellation and the high-pass filter into hold during defects.
Fig 10. Bit recovery block diagram
0x3000 0000 - 0x3000 024C: the decoder’s own registers - used to configure the
channel decoder, and the functionality they control is described in detail in this section.
0x3000 02A0 - 0x3000 0374: the decoder immigrant registers - used to control parts of
the SAF784x that do not have their own AHB interface (they are not used to control the
decoder channel decoder).
D1
D2
D3
D4
ANALOG
BLOCK
One chip CD audio device with integrated MP3/WMA decoder
Rev. 02 — 9 May 2008
AGC
AOC
ADC
6-bit
CONDITIONING
SIGNAL
BLOCK
Figure
10.
BIT SLICER
PLL AND
SAF784x
© NXP B.V. 2008. All rights reserved.
to demodulator
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