SAF7849HL/M295,557 NXP Semiconductors, SAF7849HL/M295,557 Datasheet - Page 64

• Manufacturer Part Number: SAF7849HL/M295,557
• Description: IC AUD DECODER 144LQFP
• Manufacturer: NXP Semiconductors
• Type: Audio Decoderr

Specifications of SAF7849HL/M295,557

• Applications: Audio CD
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 1.8V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935287932557

NXP Semiconductors
SAF784X_2
Product data sheet
6.8.3 Block decoder to segmentation manager interface
6.9.1 General
6.9.2 Interrupt generation
6.9 Segmentation manager
The alignment between the main channel and the subcode channel must be the same
each time a sector is read.
The MiMeD2 interface is the data interface between the block decoder and the SAF784x
segment manager. It is an asynchronous interface; the block decoder and SAF784x
segment manager operate in independent clock domains.
Data is transferred over MiMeD2 in bursts of one sector. The size and speed of the
transfer is determined by the settings in the OP_CTRL register. Each transaction on
MiMeD2 is accompanied by a toggle of the bld_req signal. The data and flags are updated
on each transaction.
The transfer order is:
The segmentation manager controls the flow of block-decoded data from the block
decoder and synchronous ARM system bus.
The segmentation manager consists of a 2 kB buffer, that is accessible on the ARM
subsystem bus once the entire sector has been transferred from block decoder into the
segmentation buffer.
The DMA cycle is then initiated to transfer sector data from the segmentation manager to
the ARM processor memory for MP3 decoding to commence. The DMA transfers are
expected to be continuous burst transfers to ARM processor memory and completed at
the sector boundary.
The segmentation manager register SEL_WRITE_MODE allows access to the
segmentation buffer either to the block decoder MiMeD interface or the synchronous ARM
system bus.
Remark: Access to segmentation buffer from the MiMeD interface is Write access only, or
Access only from synchronous ARM processor system bus is Read access only.
The segmentation buffer memory is 692-bit SRAM
of 32-bit words per complete sector is 692 words.
An interrupt is generated on completion of transfer of every sector from the block decoder.
The signal memory_full is used to generate an interrupt. The interrupt, once serviced by
software, can be cleared by register write to Inreq_Clr.
1. Main data: 1176 word16 (2352 bytes)
2. Flags data (optional): 148 word16 (296 bytes)
3. Subcode data (optional): 57 word16 (114 bytes)
4. Status words: two word16 (four bytes)
One chip CD audio device with integrated MP3/WMA decoder
Rev. 02 — 9 May 2008
32-bit SRAM. The maximum number
SAF784x
© NXP B.V. 2008. All rights reserved.
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