SAF7849HL/M295,557 NXP Semiconductors, SAF7849HL/M295,557 Datasheet - Page 76

• Manufacturer Part Number: SAF7849HL/M295,557
• Description: IC AUD DECODER 144LQFP
• Manufacturer: NXP Semiconductors
• Type: Audio Decoderr

Specifications of SAF7849HL/M295,557

• Applications: Audio CD
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 1.8V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935287932557

NXP Semiconductors
SAF784X_2
Product data sheet
7.15.1 Parallel-to-serial I
7.15.2 Variable sample-rate converter
7.15 Back-end audio processing
For memory-to-memory transfers, the length of the operation is specified. When half of
this length is reached, or when the end of the transfer has been reached, the CPU can be
interrupted or the CPU can poll for notification of this event.
The SDMA controller has a maximum of six channels, each channel can be configured
with its own source, destination, length and control information.
The SDMA controller is primarily dedicated from sector transfers from segmentation
manager to the ARM sub-system RAM.
The back-end audio processing entails the parallel-to-serial I
conversion for MP3 decoding and EBU data format generation.
The hardware sample-rate conversion receives inputs from a varying input source. The
input is an I
frequency into a fixed 44.1 kHz audio output signal. The block works at a fixed frequency:
16.9344 MHz (384
The audio input frequencies can range from 8 kHz to 48 kHz. The block converts the I
input signal to a signal with a fixed sampling frequency of 44.1 kHz.
The incoming I
upsampling factor N. After a variable hold, the signal is down-converted with a fixed
down-sample factor M.
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Performs memory-to-memory copies in two AHB cycles, and memory-to-peripheral or
peripheral-to-memory in three AHB cycles
Supports byte, half-word and word transfers, and correctly aligns it over the AHB bus
Compatible with ARM flow control, for single requests (sreq), last single requests
(lsreq), terminal count info (tc) and DMA clearing (clr)
SAF784x architecture supports little endian for data transfers
Contains maskable interrupts for each raw IRQ
Can operate in both master and slave modes
Capable of handling NXP I
Mono and stereo audio data supported
The sampling frequency can range (in practice) from 16 kHz to 48 kHz (16 kHz,
22.05 kHz, 32 kHz, 44.1 kHz or 48 kHz)
Two FIFOs are provided as data buffers, one for transmitting and one for reception;
the depth of these FIFOs is configurable in HDLi
Generates interrupt request
Generates two DMA requests
Controls include reset, stop, and mute options
DMA acknowledge signals
2
S stereo audio signal. The sample-rate conversion block converts the
2
S signal is stored in a buffer. The signal is upsampled by a variable
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44.1 kHz, or 67.7376 MHz / 4).
S conversion
One chip CD audio device with integrated MP3/WMA decoder
Rev. 02 — 9 May 2008
2
S format of 8-bit, 16-bit and 32-bit word sizes
2
S conversion, sample-rate
SAF784x
© NXP B.V. 2008. All rights reserved.
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