SAF7849HL/M295,557 NXP Semiconductors, SAF7849HL/M295,557 Datasheet - Page 69

• Manufacturer Part Number: SAF7849HL/M295,557
• Description: IC AUD DECODER 144LQFP
• Manufacturer: NXP Semiconductors
• Type: Audio Decoderr

Specifications of SAF7849HL/M295,557

• Applications: Audio CD
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 1.8V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935287932557

NXP Semiconductors
SAF784X_2
Product data sheet
7.2.3.1 Programming the external memory data widths
7.2.3.2 Wait-state generation
7.2.3.3 Output-enable delay programming
7.2.3 Read access to external memories
The sections below describe the step-by-step process required for setting up the static
memory interface unit registers prior to accessing the external memory.
The bank configuration register SMBCRx (x = bank number, 0 or 1), is used to describe
the bus width. The SAF784x can only support an external data bus width of 16-bits. If,
during a data transfer requested by the internal ARM, the external data width is narrower
than the ARM bus data width, several interface bus cycles may be required to complete
the transfer. For example, if the external memory data bus is 16-bits wide, and a 32-bit
read is requested by the ARM, the AHB bus is stalled until the static memory interface unit
has fetched the two half words.
The wait-state assertion registers are SMBWST1Rx and SMBWST2Rx. Note that ‘x’
denotes the bank number (0 or 1).
The wait-state time is crucial, as the internal AHB bus cycles are scaled with respect to
the access times of the external memory. The highest number of wait-states that can be
asserted is 31 system clock cycles. The maximum AHB clock frequency for the SAF784x,
is 76 MHz.
Hence the maximum access time that can be supported for this implementation of
wait-state register is 13 ns 31 cycles. The minimum wait-state assertion time is when the
wait-state field in the register is 0 and the hardware asserts a wait time of 2
is the fastest external memory access time.
This is an important parameter to consider when selecting the memory type to interface
with the static memory interface unit.
Each wait-state register has a particular importance for the following actions:
SMBWST1Rx when performing read transfers from external memory; SMBWST2Rx when
performing write transfers to external registers.
An example of the effect of wait-state assertion when reading from external memory is
shown in
The output enable can be programmed, at the time it needs to be active. This is typically
after the memory has been selected, by toggling the chip-select lines. The maximum
programmable delay between when the chip-select is active and when the output-enable
activates is 15 cycles. The output-enable delay value is programmed in field WSTOEN in
register SMBCRx.
This feature is intended for memory that may not be able to provide valid output
immediately after the chip-select lines are active. Note that the output-enable is
de-asserted at the same time as the chip-select lines at the end of a transfer.
Remark: The output-enable delay programmed in WSTOEN must be less than the
programmed wait-state. Note that the external memory access times are determined by
the wait-states and not by the output-enable delay.
Figure
38.
One chip CD audio device with integrated MP3/WMA decoder
Rev. 02 — 9 May 2008
SAF784x
© NXP B.V. 2008. All rights reserved.
13 ns. This
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