SAF7849HL/M295,557 NXP Semiconductors, SAF7849HL/M295,557 Datasheet - Page 12

• Manufacturer Part Number: SAF7849HL/M295,557
• Description: IC AUD DECODER 144LQFP
• Manufacturer: NXP Semiconductors
• Type: Audio Decoderr

Specifications of SAF7849HL/M295,557

• Applications: Audio CD
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 1.8V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935287932557

NXP Semiconductors
SAF784X_2
Product data sheet
Fig 5.
pad_clk3v3
Analog clock generation
PADS
6.2 Analog clock generation
register CLKGEN
CNTRL[3]
To help users set up the correct gain and DC offset for each particular mechanism, an eye
pattern monitor facility is included. This consists of a high frequency buffer amplifier
whose input can be selected to monitor various important nodes within the analog RF
path. The monitor point is controlled by register RFControl1[6:4] field RFMONSEL. The
output of the buffer drives HF_MON pin (pin 7). This register also controls the roll-off
frequency of the noise filter which is in front of the 6-bit ADC in the RF path.
Various blocks within the analog RF path can be powered down if required, including the
complete path. These power-down bits are controlled by register RFControl2[5:0].
In addition, the 6-bit RF ADC can be stand-alone tested in application mode, or a separate
external RF path IC can be connected to SAA7834 by selecting bit 1 of register
RFBypassSel. The input for the RF signal is then via pin HF_MON. In this mode the
central diode summing circuit, RF AMP1, high-pass filter and RF AMP2 are all bypassed.
OSC
OSC
The SAF784x consists of two analog phase-locked loops. The 67 MHz PLL is dedicated to
the channel decoder. The 152 MHz PLL is dedicated to the remaining functionality. The
clock strategy for the SAF784x is intended to address areas that are prone to noise effects
register CLKGEN
CNTRL[4]
0
1
2
register CLKGEN
CNTRL[5]
0
1
One chip CD audio device with integrated MP3/WMA decoder
Rev. 02 — 9 May 2008
AnaClockPLLControl[3]
CLOCK MULTIPLIER
CLOCK MULTIPLIER
VARIABLE RATIO
register CLKGEN
register CLKGEN
CNTRL[1]
CNTRL[2]
register
8
AnaClockPLLControl[0]
adac_in_8_clk
register CLKGEN
CNTRL[0]
register
used for internal test
used for internal test
0
1
0
1
AUDIO
ADC
DAC
HF
ANALOG to DIGITAL
pad_clk1v8
(used for
internal test)
lfadc8m_clk
(digital servo)
micro_clk (152 MHz)
sys32k_clk
(real time clock)
SAF784x
© NXP B.V. 2008. All rights reserved.
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