SAF7849HL/M295,557 NXP Semiconductors, SAF7849HL/M295,557 Datasheet - Page 68

• Manufacturer Part Number: SAF7849HL/M295,557
• Description: IC AUD DECODER 144LQFP
• Manufacturer: NXP Semiconductors
• Type: Audio Decoderr

Specifications of SAF7849HL/M295,557

• Applications: Audio CD
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 1.8V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935287932557

NXP Semiconductors
SAF784X_2
Product data sheet
7.2.1 SMIU operation modes
7.2.2 Selecting the memory banks
The static memory interface unit can connect to two external memories. Each of these two
memories can be accessed sequentially. The static memory interface unit consist of
memory banks that map the external memories to the main system memory address
space. The versatility of the static memory interface unit enables access to a wide range
of memory types with different memory access times.
The static memory interface unit only supports asynchronous memory types that do not
require the use of a system clock.
Each of the two memory banks is capable of supporting the following memory types:
Each of the above memories can be configured to either 8-bit or 16-bit external memory
data paths. The static memory interface unit has been configured to support only little
endian operation.
The access to the memory begins by asserting the chip-select lines to each of the two
memory banks supported.
The polarity of the chip-select lines can be programmed to be either active HIGH or active
LOW (default).
A memory bank is selected by the ARM addressing the static memory interface unit. This
is achieved on the SAF784x as follows:
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AMBA AHB-compliant
Asynchronous burst mode read access from burst mode ROM and Flash devices
Asynchronous page mode read access in non-clocked memories
8-bit and 16-bit wide data paths
Independent configuration of two memory banks, with maximum access of 2 MB each
Programmable wait-state up to a maximum of 31. This parameter influences the
response times from external memory, typically access times
Programmable output-enable and write control-enable delays (15 cycles maximum)
Byte lane select outputs for eight bits or 16 bits; this can be a useful feature if access
is only required for either lower or upper bytes of data width
Little endian configuration: this has been fixed
Programmable chip-select polarity
SRAM/PSRAM
ROM
Flash EPROM
Burst ROM memory
ARM AHB address[27:26] = 0, 0 selects bank 0
ARM AHB address[27:26] = 0, 1 selects bank 1
One chip CD audio device with integrated MP3/WMA decoder
Rev. 02 — 9 May 2008
SAF784x
© NXP B.V. 2008. All rights reserved.
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