SAF7849HL/M295,557 NXP Semiconductors, SAF7849HL/M295,557 Datasheet - Page 33

• Manufacturer Part Number: SAF7849HL/M295,557
• Description: IC AUD DECODER 144LQFP
• Manufacturer: NXP Semiconductors
• Type: Audio Decoderr

Specifications of SAF7849HL/M295,557

• Applications: Audio CD
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 1.8V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935287932557

NXP Semiconductors
SAF784X_2
Product data sheet
6.5.5.7 Internal lock flags
6.5.5.8 Format of the measurements signal Meas1 on pin CL1
The jitter measurement is absolute reference, because it relates directly to the EFM bit
error rate if the disc noise is gaussian.
The fourth signal that can be monitored are three flags in the PLLLockStatus register: the
internally generated inner lock signal FLock, the internally generated lock signal InLock
and a LongSym(bol) flag when run length 14 is detected (run length too high).
In automatic mode, the FLock and InLock flags determine what type of PLL capture aid is
used.
Table 7.
This signal is output via pin CL1 (pin 97) and comprises three measurement signals
multiplexed together. The format is shown in
The data is sent in a serial format. It consists of a pause, followed by a start bit, followed
by data bits.
Bit length: four system clock periods; frame length: 64 bits.
Table 8.
FLock flag
0
1
x
Bit
0
1 to 10
11
12
13 to 22
23
24
25 to 32
33, 34, 35
Fig 18. Format on measurement pin CL1
•
•
•
•
•
Analog preamplifier
ADC
Limited bandwidths in this device
Limited PLL performance
Influenced by internal noise filter, asymmetry compensation and equalizer
Determining the current PLL capture mode
Data format on measurement pin CL1
One chip CD audio device with integrated MP3/WMA decoder
Rev. 02 — 9 May 2008
pause
InLock flag
0
0
1
Value
'1'
jitter(9) to jitter(0)
'0'
'1'
pllfreq(9) to pllfreq(0)
'0'
'1'
asym(7) to asym(0)
'0'
start bit
Figure 18
data bits
and
001aag322
Table
Capture mode
outer-lock aid
inner-lock aid
in-lock
Description
start bit
first sample of jitter word
intermediate start bit
PLL frequency word
intermediate start bit
slicer level
‘000’
8.
[1]
SAF784x
© NXP B.V. 2008. All rights reserved.
[2]
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