PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 103

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
10.3.1 PCI Capabilities
10.2 IR Remote Control Receiver and Blaster
10.3 PCI-2.2 & XIO-16 Bus Interface Unit
This allows use of GPIO for a variety of functions.
PNX15xx/952x Series uses the GPIO pin event sequence timestamping mechanism
and software to interpret remote control commands. The event sequence
timestamping can resolve events on signal edges with 75 ns accuracy. A sequence of
events followed by a period of inactivity causes generation of an interrupt. Software
then interprets the ‘character’ by looking at the event list consisting of (time, direction)
encoded in memory.
This allows interpretation of a wide variety of Remote Control protocols. The NXP
RC-5, RC-6 and RC-MM remote control protocols are all decoded with this
mechanism, provided that the RF demodulation is performed externally. Most other
Consumer Electronic vendor remote control protocols can be supported by
appropriate software.
Similarly, the event generation mechanism can be used to implement IR blaster
capability. In this case, the modulator is included - the software generated pulses can
be superimposed on an internally generated carrier.
There are some speed considerations with this mechanism. Each character
communicated generates at least one interrupt, and possibly more if the number of
edge events exceeds the FIFO size. Hence, this mechanism is suitable only for
protocols that use frequencies up to a few 10’s of kHz, with low character repetition
rates, and not for high speed protocols.
PNX15xx/952x Series contains an expansion bus interface unit ‘PCI/XIO-16’ that
allows easy connection of a variety of board level memory components and
peripherals. The bus interface is a single set of pins that allows simultaneous
connection of 32-bit PCI master/slave devices as well as separated address/data
style 8- and 16-bit micro processor slave peripherals and standard (NOR) or disk-
type (NAND) Flash memory.
The bus interface unit contains a built-in single-channel DMA unit that can move
blocks of data to or from an external peripheral (PCI bus master or slave) to or from
PNX15xx/952x Series DRAM. The DMA unit can access PCI as well as 8- and 16-bit
wide XIO devices. The DMA unit packs XIO device data to/from 32-bit words, so that
no CPU involvement is required to pre/post process data.
PNX15xx/952x Series complies with Revision 2.2 of the PCI bus specification, and
operates as a 32-bit PCI master/target up to 33 MHz.
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50% of the pins will have a ‘low’ reset value
50% have a ‘high’ reset value
Rev. 4.0 — 03 December 2007
PNX15xx/952x Series
Chapter 2: Overview
© NXP B.V. 2007. All rights reserved.
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