PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 706

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
5.3 Initialization
After reset, the LAN100 software driver must initialize the LAN100 hardware. During
initialization the software must:
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Depending on the PHY connected to the LAN100, the software must initialize
registers in the PHY via the MII Management Interface. The software can read and
write PHY registers by programming the MCFG, MCMD, and MADR registers of the
LAN100. Write data should be written to the MWTD register; read data and status
information can be read from the MRDD and MIND registers.
The LAN100 supports RMII and MII PHYs. During initialization, software must select
MII or RMII mode by programming the Command register. After initialization, the RMII
or MII mode should not be modified.
Transmit and receive DMA engines should be initialized by the device driver,
allocating the descriptor and status arrays in memory. Real-time transmit,
non-real-time transmit, and receive each have their own dedicated descriptor and
status arrays. The base addresses of these arrays must be programmed in the
TxDescriptor/TxStatus, TxRtDescriptor/TxRtStatus and RxDescriptor/RxStatus
registers. The number of descriptor structures in an array should match the number of
status structures.
Please note that the Transmit Descriptor Structures are 16 bytes each while the
Receive Descriptor Structures and status structures of both receive and transmit are
8 bytes each. All descriptor arrays must be aligned on 4-byte boundaries; status
arrays must be aligned on 16-byte boundaries. The number of descriptors in the
descriptor arrays must be written to the TxDescriptorNumber,
TxRtDescriptorNumber, and RxDescriptorNumber registers using a –1 encoding, that
is, the value in the registers is the number of descriptors minus one. For example, if
the descriptor array has 4 descriptors, the value of the number of descriptors register
should be 3.
After setting up the descriptor arrays, packet buffers must be allocated for the receive
descriptors before enabling the Receive Datapath. The Packet field of the receive
descriptors must be filled with the base address of the packet buffer of that descriptor.
Among others, the Control field in the receive descriptor must contain the size of the
data buffer using –1 encoding.
The Receive Datapath has a configurable filtering function for discarding or ignoring
specific Ethernet packets. The filtering function should also be configured during
initialization.
After a hard reset, the soft reset bit in the MII Interface will remain asserted. Before
enabling the LAN100, the soft reset condition must be removed.
Configure the PHY via the MII Management Interface (MIIM)
Select RMII or MII mode
Configure the transmit and receive DMA engines
Configure the host registers (MAC1,MAC2, etc.) in the MII Interface
Remove the soft reset condition from the MII Interface
Enable the receive and Transmit Datapaths
Rev. 4.0 — 03 December 2007
Chapter 23: LAN100 — Ethernet Media Access Controller
PNX15xx/952x Series
© NXP B.V. 2007. All rights reserved.
23-706