PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 538

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 7: Audio In Data Bus Arbiter Latency Requirement Examples — 16-Bit Data Examples
Table 8: Audio In Data Bus Arbiter Latency Requirement Examples — 32-Bit Data Examples
PNX15XX_PNX952X_SER_N_4
Product data sheet
CapMode
2 Channels
Stereo
2x16 bits/sample
Stereo
2x16 bits/sample
Stereo
2x16 bits/sample
CapMode
2 Channels
Stereo
2x32 bits/sample
Stereo
2x32 bits/sample
Stereo
2x32 bits/sample
f
44.1
48.0
96.0
s
3.8 Error Behavior
3.9 Interrupts
f
44.1
48.0
96.0
(kHz)
s
(kHz)
shows the required data bus arbitration latency requirements for a number of
common operating modes, for 2 channels. The right column in
nature of the resulting 64-byte burst data bus requests.
In the Raw Mode however, the sampling is much faster. One eight bit byte is sampled
every SCK. Hence one 32 bit word (4 bytes) are transferred every four clocks. So for
example if the sample clock SCK is about 25 MHz, then the bandwidth requirement
would be 40 MBytes per second. Obviously this requirement is much higher than in
the usual serial mode for this block.
If either an OVERRUN or HBE error occurs, input sampling is temporarily halted and
incoming samples will be lost. In the case of OVERRUN, sampling resumes as soon
as the control software makes one or more new buffers available through an ACK1 or
ACK2 operation. In the case of HBE, sampling will resume as soon as the data in the
FIFO can be written to memory. HBE and OVERRUN are ‘sticky’ error flags meaning
they will remain set until an explicit software write of logic ‘1’ to ACK_HBE or
ACK_OVR is performed. See
The AI_STATUS register provides all sources of Audio In generated interrupt:
BUF1_FULL, BUF2_FULL, HBE and OVERRUN. All interrupts sourced by Audio In to
the chip level interrupt controller are level triggered. An interrupt will be generated
from Audio In only if the corresponding interrupt enable bit is set in the AI_CTL
register. For example, to assert an interrupt to the system upon the occurrence of a
bandwidth error (HBE asserted), set the HBE_INTEN bit to logic ‘1’. See
T (nS)
22,676
20,833
10,417
T (nS)
22,676
20,833
10,417
Rev. 4.0 — 03 December 2007
Max Arbiter Latency
(8*T) (uSec)
181.408
166.66
83.34
Max Arbiter Latency
(16*T) (uSec)
362.816
333.328
166.672
Section 4. on page
Access Pattern
1 64-byte request
minimally every 181.408uS
1 64-byte request
minimally every 166.66 uS
1 64-byte request
minimally every 83.34 uS
PNX15xx/952x Series
16-541.
Access Pattern
1 64-byte request
minimally every 362.816 uS
1 64-byte request
minimally every 333.328 uS
1 64-byte request
minimally every 166.672 uS
Chapter 16: Audio Input
Table 7
© NXP B.V. 2007. All rights reserved.
shows the
Section
16-538
4..