PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 158

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
Figure 2:
extracted
for DFT
PLL Block Diagram
clk_in
(xtal_clk)
2.2.1 PLL Specification
Fin
100MHz F
A PLL consists of a Voltage Controlled Oscillator (VCO) and a Post Divide (PD)
circuit, as presented in
The frequency from the VCO, F
F
The bit width of N, M, P is 9, 5 and 2 bits respectively. The N, M and P bits are
programmable register bits in the Clock module control registers, PLL0_CTL and
PLL1_CTL. PLL2_CTL does not allow to control the P parameter since it is fixed to
‘1’, i.e. divides F
interface.
Remark: Using a value of 0 for either M or N could lead to undesirable behavior. For
that reason, setting either M or N to 0 will result in a value of 1 being used for both M
and N. Assuming the P value is set to 0, this will result in a PLL output frequency of 27
MHz.
PLL Limitations
The following equations must be met
General Recommendations
F
F
2MHz F
2MHz F
/M
VCO
VCO
out
•
5
Keep M with low values
=
Fpd
can be post divided by 1, 2, 4 and 8 according to the following equation:
=
F
---------- -
2
27MHz
vco
P
in
pd
vco
150MHz
PD
27MHz
600MHz
VCO
Rev. 4.0 — 03 December 2007
---- -
M
N
by 2, to ensure a 50% duty cycle clock on the DDR SDRAM
Figure
FILTER
LOOP
PLL
/N
2.
9
VCO
can be determined as follows:
VCO
PNX15xx/952x Series
Fvco
Chapter 5: The Clock Module
/P
2
Fout
© NXP B.V. 2007. All rights reserved.
clk_out
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