PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 789

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
2. Summary of Native Pixel Formats
Table 1: Native Pixel Format Summary
PNX15XX_PNX952X_SER_N_4
Product data sheet
Name
1 bpp indexed
2 bpp indexed
4 bpp indexed
8 bpp indexed
RGBa 4444
RGBa 4534
RGB 565
RGBa 8888
packed YUVa 4:4:4
packed YUV 4:2:2 (UYVY)
packed YUV 4:2:2 (YUY2, 2vuy)
planar YUV 4:2:2
semi-planar YUV 4:2:2
planar YUV 4:2:0
semi-planar YUV 4:2:0
semi-planar 10-bit YUV 4:2:2
semi-planar 10-bit YUV 4:2:0
Packed 10-bit YUV 4:2:2(UYVY)
(1) The VIP is capable of producing RGB formats, but not when performing horizontal scaling.
(2) Shown are the 2D Drawing Engine frame buffer formats where drawing, rasterops and alpha-blending of surfaces can be
accelerated. The 2D Drawing Engine host port also supports 1 bpp monochrome font/pattern data, and 4 and 8-bit alpha
only data for host initiated anti-aliased drawings.
Table 1
subsystems that support them.
The layout shown in
unit size (8, 16 or 32-bit) load operation, regardless of the PNX15xx/952x Series
endian mode of operation.
Note
CLUT entry = 24-bit color + 8-bit alpha
16-bit unit, containing 1 pixel with alpha (1)
16-bit unit, containing 1 pixel, no alpha
32-bit unit, containing 1 pixel with alpha (1)
32-bit unit containing 1 pixel with alpha
16-bit unit, 2 successive units contain 2
horizontally adjacent pixels, no alpha
3 arrays, 1 for each component
2 arrays, 1 with all Ys, 1 with U and Vs
3 arrays, 1 for each component
2 arrays, 1 with all Ys, 1 with U and Vs
2 arrays, 1 with all Ys, 1 with U and Vs
3Ys are packed in 4 Bytes and 3 sets of
UV pixels are packed in 8 Bytes
2 arrays, 1 with all Ys, 1 with U and Vs
3Ys are packed in 4 Bytes and 3 sets of
UV pixels are packed in 8 Bytes
6Ys and 3UVs are packed in 16 Bytes.
and
Figure 1
Rev. 4.0 — 03 December 2007
Figure 1
summarize the native pixel formats and image hardware
is the way that a unit ends up in a CPU register given a
VIP
Out
(1)
(1)
x
x
x
x
x
PNX15xx/952x Series
MPG
Out
x
MBS
In
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Chapter 28: Pixel Formats
MBS
Out
x
x
x
x
x
x
x
x
x
x
x
© NXP B.V. 2007. All rights reserved.
2D Draw
Eng (2)
x
x
x
x
x
x
QVCP
In
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
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